I have looked through the ISA spec and searched the internet for the answer to this, but I could not find it.
In the RISC-V ISA, should negative numbers be represented with one's complement or two's complement? Or, is this decision left to implementors?
The reason I ask is that I am writing an RV32I simulator, and this would affect how I store negative numbers in the simulated memory, for example.
The RISC-V architecture requires twos-complement integer arithmetic. This can be most directly seen from the fact that it specifies a single addition instruction, not a pair of signed and unsigned addition instructions. In twos-complement arithmetic, signed and unsigned addition are the same operation; in ones-complement (and sign-magnitude) they are not the same.
It appears to me, skimming the architecture manual, that the authors considered the choice of twos-complement integer arithmetic too obvious to bother mentioning. There hasn't been a CPU manufactured in at least 25 years that used anything else.
The user-level ISA manual (page 13) notes that bitwise NOT rd, rs1 may be performed by XORI rd, rs1, -1, which would imply two's complement, if I see things correctly: XORing with the one's complement of -1 would not invert the least significant bit, while it would work correctly in two's complement.
Yes, the RISC-V instruction set architecture (ISA) mandates two's complement:
The base integer instruction sets use a two’s-complement representation for signed integer values.
(Section 1.3 RISC-V ISA Overview, page 4, The RISC-V Instruction Set Manual. Volume I, 2019-06-08, ratified)
General purpose registers x1–x31 hold values that various instructions interpret as a collection of Boolean values, or as two’s complement signed binary integers or unsigned binary integers.
(Section 2.1 Programmers' Model for Base Integer ISA, page 13, The RISC-V Instruction Set Manual. Volume I, 2019-06-08, ratified)
