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Questions tagged [instruction-set]

Use for questions related to Instruction Set Architectures, ISA. For questions related to the inner workings of a CPU, use [cpu-architecture] instead.

An instruction set is a specification for a set of machine-readable instructions, or CPU instructions. An instruction set exists for all processing units including Graphics Processing Cores, Networking Card Processors as well at the CPU. The phrase "Instruction Set" usually implies the CPU type.

Each digital logic process which a processor can perform has an binary instruction code which caused the CPU to execute that exact instruction. An assembly language translates mnemonics into instruction codes. Instruction codes are likely to differ between different processor architectures. For example, the x86_64 instruction set for Intel CPU's includes additional 64 bit instructions (among others) for manipulating data 64 bits wide inside the CPU's core, which is an extension to the x86 32 bit capabilities of previous Intel CPU generations.

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How to read/pronounce a MIPS load-byte instruction in English?

In MIPS instruction set, we have instructions like "LB R1, 0(R2)", which means "load one byte from the memory address whose base address is stored in R2 register and plus an offset of 0, load this byte to register R1". I am not an English native…
user19470144
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Is it possible to implement subroutine call without a stack nor indirect addressing?

is it possible to use subroutine with a cpu that doesn't feature indirect addressing nor a way to store the program counter, it would only feature : 2 register A and B ( and a status register for carry and zero flag) And those instructions: load…
stuart19
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What is the smallest x86_64 Hello World ELF binary?

I tried to write the smallest possible x86_64 ELF hello world program by hand, but I receive a Segmentation fault when trying to run it. gdb says: During startup program terminated with signal SIGSEGV, Segmentation fault. Here is the…
DieDummheitInPerson
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How are instruction sets standardized?

My understanding is the AMD64 was invented by AMD as a 64 bit version of x86. New instructions are added by both AMD and Intel (because those are the only two companies that implement AMD64). In effect, there is no central standard like there is in…
Badasahog
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Does $ra returns the address of current instruction or the next instruction?

I am very confused in the concept of returning address by $ra. Does it return the address of the current instruction being executed or the instruction to be executed next? For explanation please use the following code, Consider a code fragment…
user379888
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Would an Instruction Set Architecture benefit from both an ADC and SBC, or could all carry instructions repeat the previous type?

I'm creating an instruction set with only 16 instructions (4 bits opcode, 4 bits immediate), and as such am wondering if I could replace having both ADC (Add-with-carry) and SBC (Subtract-with-carry) with RWC (Repeat-with-carry). RWC would function…
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Why left shift instruction has two names (SAL and SHL) in x86-64 ISA?

I know that logical left shift and arithmetic left shift perform the same operation of multiplying the number with 2k when shifted by k bits. In x86-64 ISA, there are two instructions for logical left shift shl and arithmetic left shift sal. When…
KRS Nandhan
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How to resolve ambivalence in x64 assembly?

I'm writing an assembler. I always thought that assembly had a 1:1 correspondence between a certain assembly instruction and corresponding instruction, so I thought it would be fairly easy to write one. But after actually reading the Intel 64…
Coffee Muffin
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Is there an x86 assembly instruction that does both 'xadd' and 'adc reg,0'?

I've recently learnt about XADD and I had no luck at looking up on google. Does an instruction like XADD that also adds the carry flag exist? (ex. XADC) Or am I forced to do it with two different instructions? I'm on Ubuntu and I'm using NASM in 64…
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PowerPC opcode table?

I am interested in developing a PowerPC emulator for my own learning purposes. I've found a fair amount of resources about programming in PowerPC assembly, but after quite some time looking, I haven't been able to find an instruction/opcode mapping…
Delan Azabani
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RISCV - How are jump instructions PC-relative?

In the RISC-V Unpriviliged spec V20191213, the following is stated, (page 21) The unconditional jump instructions all use PC-relative addressing to help support position-independent code. Looking at the definition of the JALR instruction, The…
zeke
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Can a “PUSH” instruction's operation be performed using other instructions?

It currently seems to me that the only reason we have instructions like “Push” is to replace multiple MOV, and arithmetic instructions with a single instruction. Is there anything “PUSH” does that cannot be accomplished by more primitive…
Tyler
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How to add custom instruction to RISCV cross compiler?

I cloned riscv-tools (https://github.com/riscv/riscv-tools) and riscv-gnu-toolchain ( https://github.com/riscv/riscv-gnu-toolchain) and was able to get Spike, pk, and the cross compiler (riscv64-unknown-elf-gcc) to work. I want to extend this and be…
mr_broccoli
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What do the MIPS load word left (LWL) and load word right (LWR) instructions do?

I've been reading into the MIPS instruction set lately when I came across two unusual instructions that I've not seen in other instruction sets. I've looked around to find a decent explanation of what exactly the instructions do, but all I've been…
Pharap
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How to represent the product of multiplication instructions in RISCV?

In RISCV, we have mul t1, s1, s2 and mulh t2, s1, s2 instructions, which store the lower 32-bits of the product and upper 32-bits of the product respectively. If I need to use the product, should I do add t0, t2, t1? Thank you!
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