Time stamp in VHDL

Question

is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp()

score 12 · Accepted Answer · answered Dec 03 '13 at 15:40

12

Yes there is. Use the keyword now.

You can print the simulation time using VHDL Attributes:

report "current time = " & time'image(now);

You can also store the current time to a variable:

variable v_TIME : time := 0 ns;
v_TIME := now;
-- STUFF HAPPENS
v_TIME := now - V_TIME; --used to find delta time

answered Dec 03 '13 at 15:40

Russell

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I tried the first function but getting following error: **Function 'now' is not synthesizable**. Is there any library for this function or something else to solve the problem? – Digeek Dec 03 '13 at 15:56
5

@Afzal, Woah there, you said simulation time.... Do NOT try to synthesize anything having to do with time. I have personally tried never putting `now` in any synthesizable code, but it might be possible. I would surround it with `synthesis translate_off` and `synthesis translate_on` just to make sure the tools dont try to build it. – Russell Dec 03 '13 at 16:04
Actually I want to see on the console at which time a process is entering from one state to another but Xilinx ISE giving this synthesis error. – Digeek Dec 03 '13 at 16:11
Even if you surround it with synthesis translate_off and on? If that's the case then I guess you cannot do that... might just need to use the Modelsim waveform to get the times manually. – Russell Dec 03 '13 at 16:26

score 9 · Answer 2 · answered Dec 04 '13 at 15:20

If you want to know the time within your synthesised design, you will have to manage that yourself. For example, a free-running counter clocked from the same clock as the rest of your logic can be used to capture the time of particular events into registers. You could then transfer those registers periodically over some interface to a host PC or similar, or use an embedded logic analyser.

now is a purely simulation only construct, which tells you the simulation time to whatever resolution the simulator is set to. The real hardware has no concept of real time, only clock cycles, and has no standardised interface for accessing a console, so being able to synthesise report time'image(now) is not even remotely an option.

Time stamp in VHDL

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