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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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VHDL 3 Bit Counter: Error Message 3363, 1408

I want to to implement a 3 bit counter in VHDL which has a circuit schematic shown in the figure. https://i.stack.imgur.com/OoD7F.jpg When I implement the code I got the following error messages: --Actual associated with Formal OUT mode Signal 'Q'…
Umit Guden
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how to get a T flip flop simulation waveform using Xilinx ISE design suite

I tried to simulate a TFF using Xilinx ISE web pack and ModelSim using following block diagram and structural Code was written using VHDL. But I am unable to get the correct waveform. Due to the T-flip flop is sequential circuit, first I gave the…
munchi
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Different flipflops - different outputs for one reset input

I have 9 flipflops and one reset input. I need to set outputs of 8 flipflops to 0 when reset is 0. And output of one flipflop to 1. This flipflop unique and never changed. How to do it? Code of flipflops: library IEEE; use…
levshkatov
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Encoder Debounce VHDL

For practice, I attempted to make a VHDL code to run Rotary encoder hardware. It was full with debounce, quadrature decoder and an up/down counter codes. Unfortunately, when running simulation with a testbench, my results were disappointing so I…
Nathan Piper
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Whether combinational circuit will have less frequency of operation than sequential circuit?

I have designed an algorithm-SHA3 algorithm in 2 ways - combinational and sequential. The sequential design that is with clock when synthesized giving design summary as Minimum clock period 1.275 ns and Maximum frequency 784.129 MHz. While the…
june
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VHDL flip-flop reset different than 0

is any possibility to reset flip-flop vector to different value than all 0? something like: PROCESS (clk) BEGIN IF RISING_EDGE(clk) THEN IF rst = '1' THEN ff <= INPUT_VALUE; ... This don't survive…
scarabeus
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Connecting rows in Perl after filter

I want ask you for some tips. My code looks like next few rows: #!/usr/bin/env perl while () { if (/\bSTART\b/ .. /\bEND\b/) { #$together = $_; #$together = chomp ($_); print ($_, "\n"); } } __DATA__ rubish rub START Data…
jan pastyrik
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Designing a System Timer(Porgrammable Logic Timer)

System timer Computers contain a timer containing programmable channels. Programmable channels mean timers of different durations. How to design such a circuit with four programmable channels, each disabled initially. An enable input, two channel…
Nauman Shakir
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Is it legal to have an independent if-clause for the D flip-flop reset in VHDL?

I have the following code describing some registers: DCR_WR_REGS_P: process (CLK) begin if rising_edge(CLK) then if DCR_WRITE = '1' then if C_BASEADDR(0 to 6) = DCR_ABUS(0 to 6) then …
mbmsv
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D Flip flop using JK flip flop and JK flipflop using SR flip flop

Hi was trying to write Both structural and Test bench code for D-flip flop using JK flip flop as well as JK-Flip flop using SR flip flop. but i was getting the some errors. Please anyone could help me out thanks in advance. Here is my…
Shiva
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T-Flip Flop in C - How to compact

Flip Flop Fun I've been trying to code some functions with a gamepad in c for some time. When a button is held down on the gamepad, calling vexRT[Btn4D] (the '4D' just means the fourth set of buttons in the down direction) will return either true or…
Matt Walker
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Asynchronous D FlipFlop synthesis

module dff_async(clk,r1,r2,dout); input clk,r1,r2; output reg dout; always@(posedge clk or negedge r1) begin if(r2) dout<=1'b1; else dout<=1'b0; end endmodule The above code does not synthesize, and has…
VIJETH ANCHATGERI
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DFF in verilog with a delay

I'm trying to implement the nand2tetris project in verilog and am hitting a wall using icarus verilog. In the book they implement the DFF as so, q(t) = d(t-1). The output at the current time is the input at the previous posedge clk. Here is the DFF…
greut
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Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code: module up_down_4bitcounter ( out, up_down, clk, data, reset ); //Output…
Freeda Suing
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Behavioral into FlipFlop Structural

In this code, when reset equals 1 the s becomes 1000 and when reset equals 0 the s becomes 0100 then 0010 then 0001 and it starts all over again with 1000 as the start value, only if the clock is up. library IEEE; use IEEE.std_logic_1164.all; use…
Manuel Pap
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