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Questions tagged [flip-flop]

Flip-flops (FFs) are electronic devices with two stable states. They are the simplest system capable of storing one bit of information.

Anything related to flip-flops (FFs). FFs are bistable electronic devices, i.e. devices which exhibit only two stable states. As such, they can be viewed as the simplest system capable of storing one bit of information without additional circuitry.

See Wikipedia page on flip-flops.

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(VHDL) Write a double flip flop to resolve meta stability associated with asynchronous input data

Background I'm new to VHDL and trying to understand how to code a double flip flop to handle metastability associated with a user pressing a button on my fpga board (Cyclone V). I understand the logic behind using a double flip flop to stabilize the…
bsheps
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VHDL - Behavioral work correctly, Post Route has problem

I'm new on StackOverflow and I'm sorry for eventual error. I'm workin on VHDL and I have a problem with the Post-Place & Route. While behavioral works correctly, Post-Place & Route has problem and the result remain UNDEFINED for the all the…
ArPharazon
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in test bench of SRFF terminal showing error " ; is expected instead of identifier

I found this error in this testbench for SR FF. While I am compiling it using GHDL in terminal, it is showing the error ; is expected instead of '' I am just a beginner, so that I can't find the error. Can anyone please help me? library ieee; use…
Shareefa Fairoose
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how write an 8 bit up counter in vhdl with dataflow (structural) coding?

I am trying write a 8 bit up counter from 0 to 99 then return to 0 , with jk flip flop in VHDL, with active hdl program. but its do nothing. where is the problem? jk flip flop with asynchron reset : library IEEE; use IEEE.STD_LOGIC_1164.all; entity…
saeid gh
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Why do verilog tutorials commonly make reset asynchronous?

This question is in the context of FPGA synthesis if that makes any difference. The data sheet (iCE40UP) states that each logic cell has a D-type flop with asynchronous reset and clock enable inputs. Many verilog tutorials introduce sequential logic…
Marsh Ray
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Use generate statement to create 'n' array of registers in VHDL

I am converting an old AHDL code to VHDL, and I need to create 5 arrays of resisters using a generate statement. I've never used generate before, and after trying for a couple of hours I still can't find an answer for my problem. My initial approach…
Pedro Destri
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VHDL Process - how many flip-flops are needed

Kind on hard-simple question, i know it's general but that is exactly why i am asking... if i write a code in vhdl and i use a process which starts this way: Process(clk,x,y,x) begin ... end process is there any way which in i won't have to save…
Niki Davarashvili
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Testbench of SR Fliflop in VHDL

I wanted to implement an SR flipflop using VHDL. I wrote the code for the flipflop as well as the testbench. But the testbench doesn't compile correctly and gives errors which I can't figure out. I am using ghdl to compile. Please help. This is the…
Abhirup Mukherjee
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Synchronous vs Asynchronous logic - SR-Flipflop

I have came across a logical design where I have some questions. The first questions is whether there are two separate SR flip-flops in this design? The second question is whether a clock normally is used to propagate the inputs through the design…
user2466860
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T-flip flop in Verilog

I want to build a T-flip flop in Verilog. So far I have written the following code, but I wish they could see if it is correct please. The machine I was using to make the code is in the image. module flopJK(q,j,k,c); input j,k,c; output q; reg…
Carmen González
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Store a bitvector in flipflops instead of memory - Chisel

I would like to know the difference in usage of Reg and Mem in Chisel, and how I can decide which of these to choose in common scenarios. I would assume that Mem is the best idea when storing large amount of data, because it would store the data to…
Mrchacha
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perl extract text between SAME delimiter using flip-flop

I have been able to use flip-flop to extract text in past where I have different START & END. This time I've been having A LOT of trouble trying to extract text because I do not have different delimiters in my source file, because START & END of…
jd2000
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Is it possible to implement RS flip flop truth table in Python?

I am new to Python. i am using Spyder (pandas and numpy) to run an algorithm for data analysis. This requires implementation of an RS flip flop on two variables in the data. something like this in C: ((R_b) != FALSE) ? (*(State_pb) = FALSE) :…
VinayakR
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Flip-flop and latch inferring dilemma

Could someone explain to me why a latch would be inferred instead of a flip-flop? always_ff @ (posedge clk, negedge rst) begin if (!rst) a <= '0; end Shouldn't the fact that the always block is sensitive to a signal edge be enough to infer a…
evilpascal
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how to create a T- flip flop in ladder logic?

This is a bridge application where I need to alternate between 2 motors. Therefore, if you use motor 1 in the first raise/lower bridge cycle, you need to use motor 2 for the second bridge cycle. When the bridge is fully seated, there is a digital…
Dhananjay Ramesh
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