VHDL: Help understanding time steps/states and concurrency

Question

I'm normally a C#/Java programmer and I'm still having trouble fully wrapping my head around hardware description.

I have a register that loads in a value. Afterwards, a comparator compares the output of the register with the value '16'. If the value is less than or equal, I go to State_0, if it's greater than, I go to State_3.

I have a 'controlsignals' process running concurrently to my statetable process. For my control signals, I know that I have to set the enable for the register to high when I'm in State_2, so:

controlsignals: PROCESS (Tstep_Q)
BEGIN
    .... initialisation ...
    CASE Tstep_Q IS
    .... other states ....
    WHEN T2 => --define signals in time step T2
        enRegister = '1';

For my state table:

statetable: PROCESS (Tstep_Q, regOutput)
BEGIN
    CASE Tstep_Q IS
        .... other states ....
        WHEN T2 => 
            IF ((regOutput - 16) > 0) 
                THEN Tstep_D <= T3;
            ELSE Tstep_D <= T0;
            END IF;

And near the end of my code I have:

fsmflipflops: PROCESS (Clock)
BEGIN
    IF Clock'EVENT AND Clock = '1' THEN
        Tstep_Q <= Tstep_D;
    END IF;
END PROCESS;

reg: regn PORT MAP (somevalue, enReg, Clock, regOutput);

Since my state table and my control signals are concurrent blocks, my confusion is... will I first enable the register and then run the comparator to determine my next state, like I want my circuit to run (since the statetable is sensitive to regOutput)? Or would it be safer to create a new state after T2 where I have my comparator? Thank you in advance.

You haven't shown any declarations nor specified clock rate nor the intended target of you code. All these have a bearing on how much you can do in one clock cycle from Clock rising edge to Tstep_Q and RegOutput delay to subtract 16 and test the sign of the result, selecting a value for Tstep_D to Tstep_D setup. Without knowing clock rate, target implementation platform and widths you'll get opinions and *you* can find the answers by trial synthesis against a target platform. What part of the delay path has an entire clock period with a separate state? — , Oct 23 '16 at 18:40

score 1 · Accepted Answer · answered Oct 24 '16 at 10:58

Concurrency of the comparator

Imagine that right after the clock edge, the state signal has been updated. You've got one clock period to do a comparison and set the next state.

Your 'statetable' is being evaluated at all times.

Timing of enRegister

Doing the comparison in T2 only makes sense if you can read the output of the register in the same clock cycle as you are setting the enable. This may be a problem, but your question does not contain the information to check that.

Sensitivity list of statetable

You want this process to run concurrently, so all its inputs need to go in the sensitivity list.

It looks like you are working from a decent reference and structuring your code well. I suspect that the sensitivity list is really the problem you are having - causing odd behaviour in simulation, so I'll keep this answer short and let you try to fix that.

VHDL: Help understanding time steps/states and concurrency

1 Answers1