Do input and output ports behave like flip-flops? (VHDL)

Question

Do input and output ports in VHDL behave like flip-flops, i.e. are they updated on a rising or falling edge of a clock? Here is an example of what I mean.

entity main is
    port(
        clk : in std_logic; -- FPGA clock
        x : in std_logic; -- input signal
        y : out std_logic -- sampled input signal
    );
end entity main;

architecture RTL of main is
    signal y_q : std_logic;
begin

    y <= y_q; -- set the output

    copy : process(clk, x) is
        variable y_d : std_logic;
    begin
        y_d := x; -- continuously sample x
        if rising_edge(clk) then -- synchronous logic
            y_q <= y_d; -- update flip-flop
        end if;
    end process copy;

end architecture RTL;

The program above simply samples the input signal x, and sends it to the output y. The signal y_q is the sampled input signal x, whereas a sample is taken on every rising edge of a clock clk. However, I'm confused about the y signal - is that signal completely the same as y_q, or it is delayed by one clock cycle?

This is not a very efficient way to program a register. (A register is two sequential flipflops, aka latches, in series). It might even cause synthesis issues. — JHBonarius, Nov 20 '17 at 19:49
@JHBonarius I'm not trying to implement a register, I'm just trying to understand what happens with the signal `y`. And what do you mean by "is not a very efficient way to program a register". Can you please be more specific? — Marko Gulin, Nov 20 '17 at 19:58
@JHBonarius Huh? The `if rising_edge(clk)` block already implies an edge-triggered flip-flop (i.e, register). — , Nov 20 '17 at 20:03
Well, modern synthesis software would already do with one line only: `y <= x when rising_edge(clk);`. — JHBonarius, Nov 20 '17 at 20:06
@duskwuff I was talking about his use of the term flip-flop. A flip-flop circuit is a latch. Not a register. A register consists of two sequential flip-flop stages, with inverted clock. — JHBonarius, Nov 20 '17 at 20:07
@JHBonarius I'm not sure what are you trying to imply with registers. Can you please modify my code in a new answer in a way how you think this code should be written. P.S. I can't use the `when` statement since Xilinx ISE 14 does not support VHDL 2008. — Marko Gulin, Nov 20 '17 at 20:15
@JHBonarius I think I see what you're trying to get at, but that isn't consistent with the way the term is used in FPGA/ASIC development. In this context, "flip-flop" always means an edge-triggered structure; "latch" is used when a level-triggered structure is used (which is not common). — , Nov 20 '17 at 20:30
@duskwuff I think that's because a term has been used incorrectly for so long, that it has been kind-of accepted. That's why we should not use the term 'flip-flop' and instead use 'register' or 'latch', to avoid confusion. From an electrical engineering point of view, a flip-flop circuit is something you make in high school when you connect op two transistors using resistors (and sometimes capacitors, for oscillation operation). As simple bistable multivibrator circuit in fact. — JHBonarius, Nov 21 '17 at 09:46

score 2 · Accepted Answer · answered Nov 20 '17 at 19:48

2

y <= y_q just "wires up" y to y_q. There's no extra logic implied, so there's no delay.

Alternatively, you can just look at the RTL generated for this module! The screenshot below is from Xilinx ISE. ("fd" is the Xilinx name for a D-type flip-flop.)

answered Nov 20 '17 at 19:48

Thanks, I'm new to VHDL, I still need to learn how to use all these cool features. :) One more question - is it normal to have concurrent statements and synchronous logic within a single process, like in the example above? Or should I move the synchronous logic to a separate process? I prefer the solution as in the original post, since in that case I can use variables to implement "wires", but I'm not sure if this is a good programming practice. – Marko Gulin Nov 20 '17 at 19:54

JHBonarius · Answer 2 · 2017-11-21T09:59:15.010

Because you asked. The code below is accepted by Intel/Altera and Xilinx synthesis.

entity main is
    port(
        clk : in std_logic; -- FPGA clock
        x : in std_logic; -- input signal
        y : out std_logic -- sampled input signal
    );
end entity main;

architecture RTL of main is begin
    y <= x when rising_edge(clk);
end architecture RTL;

Yes, you can use when. You just cannot use it in a process before 2008.

score 0 · Answer 3 · answered Dec 14 '17 at 07:08

As for you question, is signal y the same as signal y_q, the answer is YES. y <= y_q; is a cocurrent assignment out of any processes, it just says the two signals y and y_q should be connected together, so of course, they are the same.

You should not write a register in this style, although your code seems right logically. You could check xilinx XST user guide, it will tell you how to describe a few kinds of registers.

Do input and output ports behave like flip-flops? (VHDL)

3 Answers3