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Questions tagged [digital-logic]

Digital logic is the representation of signals and sequencing of a digital circuit. It is the basis for digital computing. (Note: There is the Electrical Engineering Stack Exchange website which is more suited to asking questions on hardware.)

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Switching a logic gate on or off

if I have an "AND gate" with three inputs "A,B and control line C" can I control switching AND gate on or off .. just like this if C == 1 then AND gates works with input A,B if C==0 then nothing happens can this be done by any method ??
Abanoub Milad Nassief Hanna
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a combinational circuit that accepts a 4-bit number and generates a 3-bit binary number output that approximates the square root of the number

Design a combinational circuit that accepts a 4-bit number and generates a 3-bit binary number output that approximates the square root of the number. For example, if the square root is 3.5 or larger, give a result of 4. If the square root is < 3.5…
JustAStudent
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Is it neccessary to have "control unit next state register" to be FALLING edge triggered ?

Each module can be consider to have following power: [1] It can store data. [2] It can operate on the data.(arithmetic operation) some property of modules (listing just that, i am concerned with right now.) [1] all register/memory element in…
Bhuvan
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Simplifying Boolean Algebra

I am trying to prove that BC + !A!B + !A!C = ABC +!A I have attempted using De Morgan laws, and substituting X for !A!B and Y for !A!C, however I made no headway in this. I"ve alos tried gruopoing the A's like so, !A(!B+!C), however again I…
ZAX
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How is this Karnaugh Map organized?

A K-map generator generated this for me! Karnaugh Map And I`ve been trying to figure out how the values match up with one another. For eg. the value 7 on the table is seemingly identified by 01101 which is not 7, and so on and so forth.
Louis93
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conversion from binary to base 10 using floating point conversion

This is my first time posting. So here is my problem, I don't understand the following example. Binary representation: 01000000011000000000000000000000 =+(1.11)base 2x 2^(128-127) <-all questions refer to this line. • =+(1.11)base 2 x2^1 •…
user1596067
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Optimization of continuous assignment by mixing combinational and behavioral logics?

I am trying to wrap my head around a mix of combinational and behavioral logic. I've got small FPGA with 4 LEDs and a 66 MHz clock input. The idea was to make two of them glowing (one rising, one falling) and another two blinking. So I came up with…
user405725
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FPGA Basys 3 State Machine Logic with PMOD ALS Sensor

For a lab I must create the logic to use on a Digilent PMOD ALS. In the lab requirenment I cannot use the sclk signal on the sensitivity list and therefore use a state machine to create the 2.5 MHz clk signal to send to the PMOD ALS. See the code…
tiki
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D-latch time diagram with preset and clear?

I'm trying to study for an exam and I've been searching for any videos or images or pages explaining the time diagram for the D-Latch that involves the preset and clear. I'm finding a lot of results for the D flip-flop but not just the D-latch.…
user16951674
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How to introduce delay in structural verilog?

Signal "ADDR" has a setup time constraint of 1ns with respect to the rising edge of signal "WR". During every new clock cycle, I need to assign a value to "ADDR" and then make "WR" 0->1 after 1ns. The clock cycle is 10ns. How do I do this in…
user2524261
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scrambling GBT data to identify counterpart

this question is FPGA-design-and-languages agnostic. I use bidirectional gigabit optical transmission lines (GBT) for communication of two distant counterparts. The GBT frame payload is 80 bits, out of them I use 64, so I have additional 16 bits for…
David Belohrad
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Truth tables, boolean expressions and circuits

I have created my truth table and drawn from this a boolean expression (f = B'A' + CA' + DC' + DB + D'CB') which I have then attempted to convert into a circuit using Quartus. I am new to digital logic and I need some help from someone wit…
david8146
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Delaying the clock by a fraction of the period

If the period of the system clock is T then how can we delay the clock by 1/4 T without using any analog device? A synthesizable VHDL code is preferred.
argasm
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Synthesizable Verilog modular shift register

I'm doing a LOTTT of pipelining with varying width signals and wanted a SYNTHESIZEABLE module wherein i could pass 2 parameters : 1) number of pipes (L) and 2) width of signal (W). That way i just have to instantiate the module and pass 2 values…
Displayname
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Verilog Subtraction and addition

I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the…
Python World
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