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If the period of the system clock is T then how can we delay the clock by 1/4 T without using any analog device? A synthesizable VHDL code is preferred.

Lundin
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argasm
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2 Answers2

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You cannot delay by any fraction of a clock period reliably using digital electronics. (Whether you code it in VHDL or Verilog or Palasm or Ella or whatever is irrelevant.)

You can delay a clock by roughly 1/2T if you use the opposite edge of the clock, but even this is not reliable. In doing so you are assuming that the mark-space ratio of the clock is close to 50:50 and that will be the case whatever the supply voltage, die temperature (temperature of the actual silicon) or process corner (speed grade of the FPGA).

The only way you can delay by less than 1/2T is to exploit the fact that any logic gate has a delay through it. However, this is a very unreliable method, because that delay will vary considerably with supply voltage, die temperature and process corner. For example easily by a factor of 3.

So, if you want to delay something by 1/4T reliably, you need a clock with period 1/4T.

Matthew Taylor
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  • A clock that I need for my tiny 8bit CPU should have three outputs:1- clk (original clock with period T). 2- enable clock (is '1' on 3/4 T and '0' on 1/4 T). 3- set clock (is only on 1/4T in the middle of period). If a 1/4T delay was possible, I could make the mentioned enable and set clocks out of the original clock by anding and oring the delay clock with the original clock. But how can I do it now when it is not possible? feel disappointed ... – argasm Mar 10 '17 at 20:32
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    Then, why not providing a `clk` to the CPU with a clock period of `4*T` and produce your enable signals with FFs clocked @ `1/T` frequency? – rascob Mar 14 '17 at 16:57
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How and if this can be done depends on your target technology, plus where and why you want to delay the clock.

In an FPGA, clocks and data on the inputs and outputs commonly need to be delayed. With Xilinx FPGAs specifically, there exist hardened macros called IDELAY and ODELAY that permit you to do this. The documentation can provide more details.

Phase offset can also be done within your logic using a PLL/MMCM/DCM (another hardened macro for synthesizing various clocks from a single input clock) to regenerate the clock locked in phase with a 90 degree offset. Again, the documentation can give you further insight.

The documentation I have linked is specific to Xilinx 7-series FPGAs, but there are similar documents for most vendors and FPGA families. If you're looking to do this in an ASIC instead, you're probably out of luck looking to avoid anything analog, as both the hardened macros I've mentioned rely on analog parts internally, just not parts that you have to design.

QuantumRipple
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