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Signal "ADDR" has a setup time constraint of 1ns with respect to the rising edge of signal "WR".

During every new clock cycle, I need to assign a value to "ADDR" and then make "WR" 0->1 after 1ns.

The clock cycle is 10ns. How do I do this in structural verilog?

user2524261
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1 Answers1

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There are many ways. I would use:

`timescale 1ns/1ps
...
assign #1.2 wr_out = wr; // (wr_out is a wire)
   or
always @(wr)
  wr_out <= #1.2 wr;  // (wr_out is a reg)

The 1.2 is to have 200ps slack.

The first one is an inertial delay, which is more in line with how most real logic behaves. (If the signal change is faster then 1.2ns it is not seen. Like a signal that gets filtered out by a capacitor)

The two second one gives a 1.2ns transport delay no matter what the waveform of wr is. (Like a chain of gates delay where the pulse travels through)

I come from a world where we do NOT change the resulting gates but if you want to add delay to a gate it is very similar:

buf #(1.2,1.2) delaybuf (out,in);

You can add such a buffer with delay, alternative you have to find the last gate in the design which outputs the signal and add a delay there.

Oldfart
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  • This seems like Behavioral Verilog. I am developing code in structural Verilog. – user2524261 Mar 14 '18 at 23:21
  • But that that case you have to add a component or set a delay in the last gate outputting the signal: **buf #(1,1) delaybuf (out,in);** I'll add that to the answer. – Oldfart Mar 14 '18 at 23:40