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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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APK installation fails with NativeHelper: Failure copying native libraries [errorCode=-113]

APK installation fails on Mediatek processors that by documentation support arm64-v8a. On other devices with Snapdragon or Exynos installation finishes successfully. So far we found two devices with following chips: Mediatek MT6762 Helio P22 (12…
raiym
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Offset an index with the value in another register ARMv8

If I am able to load a register (R5) with a value from memory + some offset using the command: LDR R5, [R12, #4] How would I go about using the value of another register (R7 =0x0004 for example) as the offset? LDR R5, [R12, &R7]
Ethan Granucci
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Interrupt triggering type (edge-triggered vs level-sensitive) mismatch

I'm writing a small OS on ARMv8 architecture with GICv3. During device initialization, I expected an interrupt to be taken to the OS. However, it's never triggered. And it turned out I misconfigured the interrupt triggering type of the device as…
Jeungwoo Yoo
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Error while compiling MOV instruction in ARM assembly

I am using RVDS6_13 compiler and my processor is Cortex X1 (HERA). For a test where I need to do a bit of assembly language programming, I am getting below error in compilation: Error: A1616E: Instruction, offset, immediate or register combination…
user3565150
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ARMv8: unaligned LDR in EL3 causes exception Data Abort

I have the following bare-metal startup code for ARMv8 on FPGA, for testing the data alignment access: .section .text.boot .global _start _start: mrs x0, mpidr_el1 and x0, x0, #0xff cbz x0, master b proc_hang master: ldr x1,…
bruin
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Adding two double precision floats in assembly language in C on a Raspberry Pi 4 with 64 bit Linux

I am learning ARMV8 assembly language on my raspberry pi 4 and I want to know the simplest way that I can add two floats whilst choosing which registers I use to store the operands. I had hoped that this code would add the values stored in variables…
user8899928
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How do I find the base address of a Translation Table for initial lookup?

I'm working on code that is able to perform at Stage 1 Address Translation at EL2 in an AArch64-based system. According to the documentation I need to store the base address of the first level of the translation table in TTBR0_EL2. However, there is…
user16603720
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Is alignment necessary for vstm on cortex r52 architecture?

1.I am working on implementing memset in assembly for cortex r52(32-bit architecture). 2.In the memset implementation, I am using vstm to zero out a memory region using this operation vstm r0!, {q0-q7} // r0 (destination array), q0 - q7 :…
omkar kale
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Find out where rop gadgets are actually loaded in memory using Ropper

I am studying ROP on Arm64, I posted my thread here Return Oriented Programming on ARM (64-bit) However a new/separate issue about choosing rop gadgets has arisen which requires the opening of a new thread. So to sum up i am studying ROP…
Sp00nc3
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Find biggest and smallest values of an array using loops

I have the following code already written and everything should be good. It suppose to find biggest and smallest values in array of size 4 using loop. I got the loops setup and everything except my output is not correct. I have a bug in line 46 that…
Zed-4
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In armv8 assembly, why does it do ldr for an address, then synch barrier, and then do ldaxr for the same address again?

I've seen this code (from arm), it is basically incrementing a variable in memory and other PEs(processing element, or thread) are doing the same thing. So it is a critical section problem multiple PEs accessing the same data on…
Chan Kim
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Instruction writeback in ARM

The ARM reference manual states: If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINEDUNPREDICTABLE What does the term 'writeback' mean in this context?
fctorial
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Assembly code within C (ARMv8 architecture)

i am working on a Cortex-A72 (Armv8) and i need to implement this pseudocode: put addr1 into X9 put addr2 into X10 for i := 0 to N − 1 do STR X0, [X9] STR X0, [X10] DC CVAC, X9 DC CVAC, X10 Following my C code: int main(){ unsigned char temp =…
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ARMv8 Assembly, How to cast integer value to float value, and how to print it?

When I try to cast an integer into a float and print it out, the value stored in that register turns to 0.000000. outI: .string "%d\n" outF: .string "%f\n" mov x20, 160 mov x1, x20 ldr …
Z Han
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ARM PMU read from another core

I would like to read/write the PMU registers of core0 pmu from core1. I would like to know if this is possible. I read in the TRM of ARM cortex A53 that these registers are memory mapped. So i assume this is possible. Could someone provide the steps…
Nfpol
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