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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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Reading Armv8-A registers with devmem from GNU/Linux shell

I want to read the values of some Cortex-A53 registers, such as D_AA64ISAR0_EL1 (AArch64) ID_ISAR5 (Aarch32) ID_ISAR5_EL1 (Aarch64) Unfortunately, I lack a little embedded/assembly experience. The documentation reveals To access the…
smoothware
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Raspberry Pi 3 Model B: How to change the Byte Order to Big Endian?

I have a Raspberry Pi 3 Model B and I switched from the 32-bit Raspbian to the 64-bit Gentoo Linux as I wanted to test some 64-bit applications. Now, I want to test an application which would access data bytes in big-endian order. I know I can do…
Saurav Kumar Sahu
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Return Oriented Programming on ARM (64-bit)

I am studying Rop on ARM (64 bit). So i am testing Rop vulnerability on my ARMv8 Cortex A-72 in order to understand how it works on Arm64. I wrote a very simple c vulnerable code: #include #include void win(unsigned magic){ …
Sp00nc3
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How to find out if an ARMv8 processor supports the AArch32 execution state?

The ARMv8 Architecture Reference Manual lists miles of special registers, some of which allow the programmer to detect the availability of CPU features at runtime. Is there such a register telling the programmer if the AArch32 execution state is…
fuz
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Any CPUID like instruction in armv8?

So I am programming in assembly ARMv8, I would like to know if there is any instruction, like in x86, to recover information about CPU. This is the information I need: (CPUID) Signature: 660f01 (CPUID) Features: MMX, AMD64, SSE, SSE2, SSE3, SSSE3,…
MustSee
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Does AArch64 need a DSB after creating a page table entry?

On aarch64 armv8 platform, single core, after we create a new page table entry, then immediately access the address: str x1, [x0] ;x1 is phy addr for pte, x0 is pte_entry ldr x2, [x3] ;x3 has VA that is mapped by above instruction My question: Does…
Leslie Li
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ARMv8 changing from el3 to el1 secure

I am trying to change from el3 to el1 secure but i keep get the processor to hang somewhere. My code is running on a Cortex-A53 (raspberry pi 3). For now I can only drop from EL3 to EL2. /* Code to try jump to EL1 secure */ MSR SCTLR_EL1, XZR MRS…
timanu90
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Retrieving clock cycles with inline ARM assembly

I'm playing around with some C reference code and it came with its own benchmarking routines. Unfortunately, the benchmarking code had a line of inline x86 assembly, and I'm trying to compile it on AArch64 ARMv8 system (a Raspberry Pi 3 if that…
werx216
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aarch64 xtn2 clearing lower half

Is there an operation similar to xtn2 but that actually clears the lower half instead of leaving it as is? I have a 128 bit vector v0 whose view as 4s is {a,x,b,y} with x and y irrelevant. I want to obtain {0,0,a,b}. If I do xtn2 v0.4s,…
potuz
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How to understand the ARMv8 AArch64 MMU table descriptor format in the diagram?

The diagram below is taken from ARMv8-A Programmer's Guide: I am a bit confused by the highlighted entry type. Let me state my current understanding first (suppose the scenario of a stage 1 translation in EL3 with granule size 4KB). In the first…
bruin
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Compile and run a 32bit binary on Armv8 (aarch64) running 64bit linux

I'am trying to compile and run a 32 bit binary on a Cortex-A72 Armv8 using gcc compiler but i am not able to do it. I followed this prior thread Having trouble compiling 32-bit binary on 64-bit linux armv8 machine and i am realized too that the -m32…
Sp00nc3
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ARMv8 Advanced SIMD: "invalid addressing mode at operand 2 -- `st1 {V1.D}[0],[x20,640]'"

I am trying to store 64 bits to memory from a V register to an address held in an X register but I get the error, "invalid addressing mode at operand 2 -- `st1 {V1.D}[0],[x20,640]". From the ARMv8 Instruction Set Overview, the operation should look…
Apple
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C++ support of _Float16

I want to do half-precision floating-point computations on Jetson AGX Xavier(with armv8.2 architecture) which supports half-precision floating-point natively. As _Float16 data type is an arithmetic data type for half-precision floating-point, I…
Sooora
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Is there an Armv8-A intrinsic for 16-byte wide VTBL?

According to my regularly used source Searchable Neon Arm Intrinsic Guide, there are only these (four classes of) intrinsics for lookup table with 8 byte target register (uint8x8 and poly8x8_t variants omitted for brevity). int8x8_t vtbl1_s8…
Aki Suihkonen
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Load-Acquire/Store-Release and interrupts

Let's say I have an atomic load-modify-store operation: 1: ldaxr x8, [x9] orr x10, x8, #1 stlxr w11, x10, [x9] cbnz w11, 1b If I understand this correctly, when this code is executed on two cores (access to the same memory…
Alexander Zhak
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