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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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What is arrangement specifier(.16b,.8b) in ARM assembly language instructions?

I want to what exactly is arrangement specifier in arm assembly instructions. I have gone through ARM TRMs and i think if it is size of Neon register that will be used for computation for e.g. TBL Vd.Ta, {Vn.16B,Vn+1.16B }, Vm.Ta This is taken from…
surajrgupta
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Floating point register corruption on ARM Cortex A57 (ARMv8) with RT_PREEMPT linux

I have a multi threaded userspace application running on RT_PREEMPT linux on ARM Cortex A57 (ARMv8). The linux version is 4.14.0 with the corresponding RT_PREEMPT patch. The below code is a simplified version to re-create the issue. When the code is…
Anup
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How to Store multiple 5-element structures from five registers in assembly of armv8/aarch64/arm64?

Now, I have five 128-bits SIMD register: v0: p0 p1 p2 p3 p4 p5 p6 p7 v1: p8 p9 p10 p11 p12 p13 p14 p15 v2: p16 p17 p18 p19 p20 p21 p22 p23 v3: p24 p25 p26 p27 p28 p29 p30 p31 v4: p32 p33 p34 p35 p36 p37 p38 p39 where pn is the pixel value.…
Gary
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Are the VBAR_EL registers saved over context switch in ARM?

I was told at one point that the VBAR_EL0/1 registers are not backed up on a context switch. I also noticed that the VBAR_EL0/1 registers are not listed here, but outside of that I'm not finding much information on it. Does this mean that the…
HardcoreHenry
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ARM V-8 with Scalable Vector Extension (SVE)

I come across this point that ARMv8 is now supporting variable length vector register from 128 bits to 2048 bits (scalable vector extension SVE). It is always good to have bigger width of register to achieve the data level parallelism. But on what…
user3476225
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Does Clang lack CRC32 for ARMv8/Aarch64?

I'm attempting to set-up CI for our Xcode cross-compiles. The cross-compiles test both ARMv7 and ARMv8. Things look good except when it comes time to link for ARMv8: clang++ -DNDEBUG -g2 -O3 -fPIC -pipe -Wall -miphoneos-version-min=7 -arch arm64 \ …
jww
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Difference between privilege level & exception level

The ARM architecture provides 3 privilege levels PL0 to PL2. While going through other documentation I found exception levels EL0 to EL3. What is the difference between privilege level & exception level. Or both are same.
Pankaj Misra
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How can I suspend, checkpoint and resume ARMv8 processes on my Mac M1?

I am writing ARMv8 assembly and running it on my Mac M1 to solve problems such as the Travelling Salesman. These programs can run for a long time (several days or weeks). Is there any way I can suspend these processes, save their state to disk and…
Chris
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ARM-SVE: wrapping runtime sized register

In a generic SIMD library eve we were looking into supporting length agnostic sve However, we cannot wrap a sizeless register into a struct to do some meta-programming around it. struct foo { svint8_t a; }; Is there a way to do it? Either clang…
Denis Yaroshevskiy
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How to set the NZCV flags to constants in a single ARMv8 instruction

I'd like to write a function that takes an ARMv8 instruction containing a condition code, and returns an ARMv8 instruction whose effect is the same as the original but with the condition inverted. Most cases are easy: If the condition code is not…
apt1002
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Device is incorrectly detected as 32bit by Android?

Huawei Honor 9S device (with Android 10) has reportedly 64bit CPU (Mediatek MT6762R Helio P22 which supports armv8l), but Build.SUPPORTED_64_BIT_ABIS is empty (String[0]) and no armv8 shared libs are extracted from AAB by Android, but armv7a…
4ntoine
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Set up stage 2 translation table ARMv8

I am working with small/basic bare-metal Hypervisor set-up that starts in EL2, and later on switches to EL1 where I have MMU set-up (using stage 1 translation) which is working. For instance the following snippet that sets-up the table. ``` uint64_t…
Milan
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Are system registers banked per processor on ARMv8-A?

Are system registers banked per processor on ARMv8? I thought they weren't, which is why they were called system registers, but I'm now confused. My understanding is that on multi-core ARMv8-A implementations different cores can be executing at…
Semepe Maple
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What is the application of the ARM unprivileged load store instructions like LDTR compared to LDR?

I came across the LDTR ARMv8 instruction today for the first time. I read its description on the ARMv8 DB manual section C3.2.5 "Load/Store unprivileged", and from what I understood it basically allows EL1 to make memory accesses with EL0…
Ciro Santilli
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Which processor part does a MOV instruction in armv8 use

Suppose I have the following instruction - MOV X5, XZR What part of the processor hardware would this MOV pseudo instruction use? What I mean is - does the MOV instruction require the use of the ALU or the Memory? It would obviously require…
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