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Questions tagged [armv8]

This tag is for questions regarding specifically version 8 of the ARM architecture - 32-bit or 64-bit. Questions about the 64-bit ARM execution state or instruction set should be tagged with [arm64].

Version 8 of the ARM architecture introduced a new 64-bit execution state (AArch64) with a new 64-bit instruction set (A64) as well as retaining and extending the existing 32-bit execution state (AArch32) and its instruction sets A32 ("ARM") and T32 ("Thumb").

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HugePages on Raspberry Pi 4

I need help about managing Hugepages on raspberry pi 4 running raspberry pi OS 64 bit. I did not find much reliable information online. First I recompiled the kernel source enabling Memory Management options --->Transparent Hugepage Support…
user13938059
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Cache hit and cache miss measurements ARMV8

I have been trying to measure cache hit and cache miss. I have been working on a Quad core Cortex-A72 (ARM v8) 64-bit SoC @ 1.5GHz. My c code to measure cache hit is: #define _GNU_SOURCE #include #include #include…
user13938059
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Problem about reading/writing memory in EL2

I am trying to read/write a memory in EL2, but it doesn't return what I want. I use kzalloc to get initialized space, then use str to write a number (0x12345678) in this space. Next, I use __pa() to get the physical address(PA) of this space. I…
irakatz
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physical addresses on the same rank/bank

I'have been trying to understand how to get two physical addresses mapped in the same bank. Given two physical addresses how can i know if they are on the same bank ? My first question is : supponing to have addr1 and addr2 with the same physical…
user13938059
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Is there a way to flush ARM cache from EL0?

I have been trying to implement a PoC code for Spectre Attack on ARMV8 (I understand most ARMV8 processors aren't vulnerable to the attack but trying to implement it anyway). I am using the asm volatile ("DC CIVAC, %[ad]" : : [ad] "r" (addr));…
Balvansh Heerekar
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How does the ARM yield instruction inform other threads that they could start, and how does it compare to WFE?

While studying WFE, I came across the YIELD instruction in the ARMv8 DB manual Section B1.3.3 "The YIELD instruction". That section says: The YIELD instruction provides a hint that the task performed by a thread is of low importance so that it…
Ciro Santilli
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How can I use .bss section of memory(for global variables) for assembly(armv8) program properly?

Here's how I wrote it on my code: .section .text fmt: .string "x \t\t ln(x)\n" sfmt: .string "%.10lf \t %.10lf\n" error: .string "Error" filename: .string "input.bin" .section .data LIM: .double…
Elo
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Armv8 address fields for cache?

I am reading, ARM Cortex-A Series Programmer’s Guide for ARMv8-A. In 11.1.2 Cache tags and Physical Addresses, There was an example for cache address fields. Example: Cache is 4-way 32KB Cache line = 16-words (64 Byte) And the address fields stated…
Mostafa
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How to generate an address size fault on ARMv8 32 bits?

I am new in ARM and I am trying to understand the theory behind address translation in order to generate an address size fault at different levels. I know that during the process from virtual address to physical address translation the…
ohskr27
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Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, most of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the…
sherrellbc
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Detect extended supersection support on arm processor at runtime

In its section on AArch32 address translation, the ARMv8 manual describes how the base physical addresses of supersections can be up to 40 bits in size when the processor supports this type of extension. I have been unable to identify a way by which…
Peter
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How to make ardrone autonomy package work on Jetson Nano?

I'm working on a Jetson Nano board and I need to connect it with a parrot ar drone 2.0, so in order to do that I would like to use the ardrone_autonomy package, but I can't do that because jetson has Ubuntu 18, which only supports ROS Melodic, which…
rooky
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In Android.mk, enabling OPENMP for arm64-v8a becomes slower?

I would like to use OpenMP in my Android program. After searching online, I edited my Android.mk and added the OpenMP flag. However, without changing any code, the program runs slower. This issues happens only when I enabled OpenMP in armv8a. ifeq…
debug_all_the_time
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How to enable MMU in QEMU (virt machine a57 cpu)

I am writing a bare-matel ARMv8 program on QEMU, but when i enable the MMU, it can't continue execute any instructions. The QEMU option is "-machine virt -cpu cortex-a57 -smp 1 -m 1G -nographic -serial mon:stdio -kernel a.bin" Here is my code…
zlp
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Assembly armv8 on mac os

I would like to assemble Aarch64 armv8 Assembly on my mac and eventually run it with qemu and maybe on a real device like a raspberry pi 2 or 4 later on. I don't know how to assemble the code I'm going to write, gcc, llvm-gcc and clang don't seem to…
L.B.
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