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The ARM reference manual states:

If a Load instruction specifies writeback and the register being loaded is also the base register, then behavior is CONSTRAINEDUNPREDICTABLE

What does the term 'writeback' mean in this context?

fctorial
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    Something like `ldr r0, [r0, #4]!` where the result of the index calculation is written back to the base register. This also applies to post-index addressing modes like `ldr r0, [r0], #4`. – fuz Feb 08 '21 at 18:27
  • @fuz What does the ldr instruction do? It isn't listed in arm64 instruction reference. https://developer.arm.com/documentation/100076/0100/a64-instruction-set-reference/a64-general-instructions/?lang=en – fctorial Feb 08 '21 at 19:08
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    @fctorial You're looking at the General Instructions. In this case you should be looking at [the Data Transfer Instructions](https://developer.arm.com/documentation/100076/0100/a64-instruction-set-reference/a64-data-transfer-instructions/ldr--immediate-?lang=en). – Michael Feb 08 '21 at 19:26
  • I'd suggest starting with some basic tutorial stuff and/or common compiler output to get familiar with the most common instructions before you dive into the full manual; the details will make more sense if you have some idea of the big picture (like what `ldr` is. It's ARM's load instruction so it's pretty fundamentally important.) – Peter Cordes Feb 08 '21 at 21:07

1 Answers1

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The "ldr (immediate)" instruction has three forms:

ldr x0, [x1, 8]
ldr x0, [x1, 8]!
ldr x0, [x1], 8

The first one should be obvious, and is the "regular" syntax.
The second one is called pre-indexing and is equivalent to:

add x1, x1, 8
ldr x0, [x1]

And the third is called post-indexing and is equivalent to:

ldr x0, [x1]
add x1, x1, 8

The situation that the manual refers to are instructions like so:

ldr x0, [x0, 8]!
ldr x0, [x0], 8

And in that case (from page K1-8255 of the G.a version):

CONSTRAINED UNPREDICTABLE behavior

If the instruction encoding specifies pre-indexed addressing or post-indexed
addressing, and n == t && n != 31, then one of the following behaviors must
occur:

•   The instruction is UNDEFINED.
•   The instruction executes as a NOP.
•   The instruction performs the load using the specified addressing mode,
    and the base register is set to an UNKNOWN value. In addition, if an
    exception occurs during such an instruction, the base register might be
    corrupted so that the instruction cannot be repeated.
•   For execution at EL0 or EL1, when EL2 is implemented and enabled for the
    current Security state and HCR_EL2.TIDCP is 1, the instruction is trapped
    to EL2 with EC value 0x0.

------ Note ------------
Pre-indexed addressing and post-indexed addressing imply writeback.
------------------------
Siguza
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