4

I'm playing around with some C reference code and it came with its own benchmarking routines. Unfortunately, the benchmarking code had a line of inline x86 assembly, and I'm trying to compile it on AArch64 ARMv8 system (a Raspberry Pi 3 if that helps).

From the context I figured out all the x86 assembly does is report clock cycles. I dug around the ARM processor docs and figured out I should probably be polling the CNTPCT_EL0 system register, and wrote the following:

unsigned long long result;
asm volatile ("mrs %0, cntpct_el0" : "=r" (result));

However, I get the following error from the assembler:

Error: selected processor does not support requested special purpose register -- `mrs r0,cntpct_el0'

So far I've tried changing the gcc flags (variations on -mcpu and -march), explicitly setting the destination register to being 64 bit, even updating binutils. What am I missing?

artless noise
  • 21,212
  • 6
  • 68
  • 105
werx216
  • 41
  • 3
  • 1
    I'm pretty sure despite the hardware in the Pi 3 being capable of running in 64-bit (AArch64) mode, it's used as a normal 32-bit ARM in practice. You need to be writing code for the ARM/Thumb ISA(s), not AArch64. – R.. GitHub STOP HELPING ICE Aug 12 '16 at 21:39
  • 2
    Are you definitely running a 64-bit kernel and userspace? AFAIK the standard Pi 3 image is still 32-bit, and that's an error message from a 32-bit assembler. Beyond that, you'll probably find that EL0 access to the PMUs isn't enabled anyway. – Notlikethat Aug 12 '16 at 21:42
  • Oh dang, I didn't even think about that. I just assumed the thing was in 64 bit mode. Thanks! – werx216 Aug 12 '16 at 22:03

0 Answers0