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The ARMv8 Architecture Reference Manual lists miles of special registers, some of which allow the programmer to detect the availability of CPU features at runtime.

Is there such a register telling the programmer if the AArch32 execution state is supported? One thing I found is ID_PFR0_EL1 which tells what variants of the AArch32 instruction set are supported, but it does not seem to say if the instruction set is supported at all.

What register or other thing am I looking for?

fuz
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1 Answers1

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You're looking for ID_AA64PFR0_EL1.

From the manual, page D13-3253:

Screenshot

And yes, there are ARMv8 CPUs that do not support AArch32 at all. Apple's A11 and later is an example.

Siguza
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  • Thanks! I must have missed this one. So I assume the Apple M1 does not support it either? – fuz Nov 22 '20 at 01:31
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    I see, so a non-AArch32 CPU would have 0000 or 0001 in all four nibbles. – Nate Eldredge Nov 22 '20 at 01:31
  • @fuz I haven't had the chance to dump this register on an M1, but I'm strongly assuming so. – Siguza Nov 22 '20 at 01:32
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    @Siguza I've just tried, but macOS Big Sur doesn't let you read this register from a user process it seems. Quite the bummer. – fuz Nov 22 '20 at 01:33
  • @fuz Given that the register is EL1-exclusive by architecture, an OS would have to trap such accesses and manually perform them. I'm not aware of _any_ OS doing that. You'd have to at least load a kext in order to access this register. – Siguza Nov 22 '20 at 01:35
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    @Siguza FreeBSD does actually. – fuz Nov 22 '20 at 01:38