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Let's say I have an atomic load-modify-store operation:

1:    ldaxr x8, [x9]
      orr x10, x8, #1
      stlxr w11, x10, [x9]
      cbnz w11, 1b

If I understand this correctly, when this code is executed on two cores (access to the same memory address), then thread A locks the resource with ldaxr. stlxr in thread B fails and operation is retried until thread A releases the lock.

But what happens if an interrupt occurs after ldaxr in main thread and interrupt handler tries to access the same memory address? Will it dead-lock or interrupt handler takes precedence and stlxr in main thread will fail when returned from the interrupt?

curiousguy
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Alexander Zhak
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2 Answers2

5

The main code's store instruction success code will indicate failure.

Broadly speaking across processor architectures, the way these work is processor dependent.  I believe that there are a number of implementation strategies would work, however.  The processor could take away a reservation on interrupt (implying it would never have to save/restore reservation state on context switch), or, could wait to take away the reservation until another ldaxr is done, or could wait until another ldaxr is done at the same cache line or same address.  With some approaches, the processor will store the location/address of the reservation, and in other approaches (i.e. maybe single core), it doesn't necessarily have to (unless it wants to verify correct usage of an ld/st pair, which are supposed to match in address and access size).

From this ARM manual, pg B-165 states :

B.6.5 Load-Exclusive and Store-Exclusive instruction constraints:

If two StoreExcl instructions are executed without an intervening LoadExcl instruction the second StoreExcl instruction returns a status value of 1.

... more details ...

(1 is the failure code and 0 is the success code.)

So, by that text, if the processor executes such a store during interrupt that will cancel any acquired reservation and thus, make the main code's store fail, regardless, perhaps of the memory addresses involved.

While the architectural requirement by the instruction set is usually fairly specific, a wide range of alternative strategies with differing trade-offs can be implemented to accomplish that.

Erik Eidt
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5

The stlxr in the main thread will fail.
ldaxr and stlxr are Load-link/Store-conditional instructions, they are lock-free, the user must be prepared to repeat the LL/SC.

Whenever an address is read using a Load Exclusive instruction, it is marked as being for an exclusive access. If an address marked as exclusive is written to using a Store Exclusive instruction, it clears the exclusive status. An attempt to write to an address not marked as exclusive using a Store Exclusive instruction will not succeed. This enables software to detect if the contents of that address have been changed since the last time it was read.

Margaret Bloom
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