ALU stands for Arithmetic Logic Unit, that performs arithmetic and logical operations for computer systems.
Questions tagged [alu]
188 questions
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Carry/Borrow in VHDL ALU
I am making a generic N-bit ALU in VHDL. I am having trouble assigning the value for the carry for addition, or borrow for subtraction. I have tried the following:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu…
Sara Fuerst
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readmemh reads values wrong
module tb_alu32();
reg clk, reset;
reg [31:0] tb_a, tb_b, tb_yexpected;
reg [2:0] tb_op;
wire [31:0] tb_result;
reg[31:0] vectornum, errors;
reg[99:0]…
CHANHO JUNG
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Turning a 1-bit ALU into an 8-bit ALU
Below is my 1-bit ALU which is proven to work. Now I would like to use this 1-bit ALU in an 8-bit ALU, and it needs to pass a testbench. So far I compiled an 8-bit ALU code, but it doesn't seem to work.
module ALUSlice(A,B,CI,M,S,F,CO); //Code for…
beatsbyse
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VHDL testbench not changing output ALU 32bit
You see, I've already finished to describe an ALU on vhdl with modelsim, however the testbench seems to not update the solution, when I see the simulation the circuit 32 bit response always says "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" I dont know what…
user145708
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VHDL program that chooses which operation to perform
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_bit.all;
use ieee.numeric_std.all;
entity multiplexer is
port (
A,B: in std_logic_vector (7 downto 0);
CI: in…
Purushottam Mukhopadhyay
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Make an arithmetic logic unit in vhdl
I need to make an arithmetic logic unit in VHDL for the pic16f684.
So the instructions for the ALU can be found in the datasheet of the pic16f684.
The instructions I need to make are the following:
These are the instructions
This is my code so far,…
Faalhaaz
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Making a 4-bit ALU from several 1-bit ALUs
I'm trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using:
component alu1 -- define the 1 bit alu component
port(a, b: std_logic_vector(1…
Logan
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Why is Cout only being accounted for during addition and not subtraction in my adder/subtractor (Verilog)
Here is my code:
module Adder_8b_df (A, B, opcode, S, Cout);
input [7:0] A, B;
input [3:0] opcode;
output [7:0] S;
output Cout;
wire [8:0] tmp;
assign tmp = (opcode[0] == 0) ? (A + B) : (A + (~B + 8'b1));
assign S = tmp [7:0];
assign…
Olivia
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Verilog HDL behavioral coding calling modules for ALU
This is my first time programming in verilog hdl and I am having trouble figuring out what is wrong with my code. I need to design a simple ALU in behavioral code.
So far I have created a subtractor and adder module.( I need to add more modules but…
DarkLink
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MIPS Hardware Multiplication ALU
Can someone please point out what I am doing wrong?
For every right-most bit of the multiplier, if I encounter a one, I add the multiplicand in the left side of the product.
Your help is appreciated.
Can't see me
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Nand2tetris ALU implementation without using Muxes
i am trying to implement Hack ALU without using muxes but i cant upload the hdl into the simulator. Any help would be appreciated. Thanks
CHIP ALU {
IN
x[16], y[16], // 16-bit inputs
zx, // zero the x input?
…
Vik Bhullar
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Arithmetic Logic Unit - Switching Function - Proof
I hope this is the correct section to ask. Since the ALU is part of a processor which is a part of computer, I think it's not too bad.
Given is an n-Bit-ALU with OM (=operating mode), control vector S=(S_0, S_1, S_2, S_3) and 2 entrace vectors…
rpbudd
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understanding of vhdl code and flow of 4 bit ALU?
I am making 4 bit ALU here i have declared entities
entity ALU is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0););
end ALU;
can you please explain that how logic vector array works there i mean syntax of
a : in STD_LOGIC_VECTOR…
nouman arshad
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Which control bit operation is performed in case of two control bit tie in ALU?
suppose we have two control input bits to ALU
zx-------zero the x input.
nx-------negate the x input.
when these both bit are set then in which order x input is manipulated or firstly which control bit get the priority as the result obtained by…
OldSchool
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How JUMP is decided based on the value of OUT-The ALU Output?
Figure from The Elements of Computer System (Nand2Tetris)
Have a look at the scenario where
j1 = 1 (out < 0 )
j2 = 0 (out = 0 )
j3 = 1 (out > 0 )
How this scenario is possible as out < 0 is true as well as out > 0 but out = 0 is false. How out…
OldSchool
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