VHDL testbench not changing output ALU 32bit

Question

You see, I've already finished to describe an ALU on vhdl with modelsim, however the testbench seems to not update the solution, when I see the simulation the circuit 32 bit response always says "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU" I dont know what did i wrote wrong on the testbench also there is a warning on the compiler about the circuit response which says

** Warning: (vsim-8683) Uninitialized out port /alu_tb/ALU_test/res(32 downto 0) has no driver. This port will contribute value (UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU) to the signal network.

and here is the testbench code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ALU_tb is        
end ALU_tb;

architecture bhv_ALU_tb of ALU_tb is
component ALU
    port(
        a, b: in std_logic_vector(31 downto 0);
        c: in std_logic;
        s: in std_logic_vector(3 downto 0);
        res: out std_logic_vector(32 downto 0));
end component;

signal a, b: std_logic_vector(31 downto 0);
signal c: std_logic;
signal s: std_logic_vector(3 downto 0);
signal re: std_logic_vector(32 downto 0);

begin 
    ALU_test: ALU port map (a => a, b => b, c => c, s => s, res => re);
process begin
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "1111";
    wait for 2 ns;
    b <= "00000000000010100111010100011110";
    a <= "00000000011010000100110011101110";
    c <= '0';
    s <= "0100";
    wait for 2 ns;
    s <= "0000";
    wait for 2 ns;
    s <= "0001";
    wait for 2 ns;
    s <= "0010";
    wait for 2 ns;
    s <= "0011";
    wait for 2 ns;
    s <= "0100";
    wait for 2 ns;
    s <= "0101";
    wait for 2 ns;
    s <= "0110";
    wait for 2 ns;
    s <= "0111";
    wait for 2 ns;
    s <= "1000";
    wait for 2 ns;
    s <= "1001";
    wait for 2 ns;
    s <= "1010";
    wait for 2 ns;
    s <= "1011";
    wait for 2 ns;
    s <= "1100";
    wait for 2 ns;
    s <= "1101";
    wait for 2 ns;
    s <= "1110";
    wait for 2 ns;
    s <= "1111";
    wait for 2 ns;
end process;
end bhv_ALU_tb;

i know the mistake seems trivial "res isn't initialized" but I've been away from vhdl way too long and honestly dont know how to fix it, any ideas?

The answer to this question is inside your component - `res` is out value, so if it is not connected to anything inside it, it is not driven from inside the module. — Staszek, May 16 '17 at 07:40

score 2 · Answer 1 · answered May 16 '17 at 08:46

Firstly

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Bad.. don't use. You don't even need them in this file. If you ever need arithmentic, use numeric_std.

Then: the error is in the component ALU, becasue that should 'drive' res. But since you did not post the code of that, we cannot help you (yet).

p.s. currently you do not need to define a component in VHDL anymore. You could just write:

ALU_test: entity work.ALU port map

VHDL testbench not changing output ALU 32bit

1 Answers1