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I am making 4 bit ALU here i have declared entities

entity ALU is
      Port ( a : in  STD_LOGIC_VECTOR (3 downto 0););
       end ALU;

can you please explain that how logic vector array works there i mean syntax of 

        a : in STD_LOGIC_VECTOR (3 downto 0);

and also

the operator =>

2- what is difference between sequential design and combinatorial design AND hierarchical design and tell me ALU CPU is coded in all of them?

nouman arshad
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1 Answers1

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can you please explain that how logic vector array works there i mean syntax of

a : in STD_LOGIC_VECTOR (3 downto 0);

this is a port declaration, consisting of

  • a - the name of the port
  • in - its direction - it supplies a signal into this entity
  • STD_LOGIC_VECTOR - its type (roughly, an array of bits)
  • (3 downto 0) its index type (4 integers in a descending range)
  • ; - a separator before the next declaration.

It's not clear from the question, what you don't understand.

the operator =>

Is not really an operator, you can't overload it for example - it's an association, associating (in a case statement) the case value on the left with the case action on the right.

You'll also see it associating parameter names with parameter values in argument lists, port maps, etc.

2- what is difference between 4 bit behavioral alu and 4 bit verdict multiplier

One can add, the other can multiply. Though I've never heard of a "verdict" multiplier.

  • `case sel is when "0000" => z<= a and b; when "0001" => z<= a or b; when "0010" => z<= a xor b;` SO 2 ASSOCIATIONS <= & => THER – nouman arshad Aug 23 '16 at 09:48
  • Then 'a' would be an output not an input. –  Aug 23 '16 at 09:49
  • <= isn't an association, it's a signal assignment. And if you want to ask anything, please edit your actual questions into the question, not in comments. –  Aug 23 '16 at 09:50
  • speacially `process (a,b,sel)` how and its assignment are these operators only used in case of CASE statement or any other use – nouman arshad Aug 23 '16 at 10:02