Highest Voted 'alu' Questions

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What is the appropriate name for this hardware multiplier? Also, where can I find documentation on it to understand what is going on?

We're doing some work on a CPU in logism in class. We're going over the ALU, and need now need to know different ways multiplication can take place. Our professor gave us two examples, one called the "Five Add Time" and the "31 Add Time" (although I…

algorithm cpu alu

asked Apr 15 '15 at 21:11

Dan

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Red output running testbench on 4-bit ALU

I'm trying to create a 4-bit ALU in Verilog that does multiplication, addition, BCD addition and concatenation. Here's my code so far: module alu4bit(A,B,S,Y); input [3:0] A, B; input [1:0] S; output [7:0] Y; reg [7:0] Y; wire [7:0] A0, A1, A2,…

verilog system-verilog alu

asked Mar 24 '15 at 17:51

Austin

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Combinational logic "IF" and "assign" statement in systemverilog

I found a very strange behaviour when design my ALU, hope someone can have a look it and tell me what is going on. Here is the code module adder ( output logic signed[31:0] y, output logic Cout, input logic signed[31:0] a, b, input logic Cin,…

system-verilog alu

asked Feb 27 '15 at 13:33

Shuaiyu Jiang

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1 bit ALU whose operations depend on carry in

I have to design a 1 bit ALU for an assignment which would then be reused to make 4 units and a 4 bit ALU. 1 bit ALU has 2 select lines and inputs A, B and a carry in. My problem is that the select lines AND the carry in flag choose what operation…

vhdl alu

asked Jan 25 '15 at 19:34

FPGA24

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Wrong output value in 8-bit ALU

I want to design an 8-bit ALU. I have written this code, but when I simulate it, the output has x value. Why did it happen? module eightBitAlu(clk, a, b,si,ci, opcode,outp); input clk; input [7:0] a, b; input [2:0] opcode; input si; input…

verilog modelsim alu

asked May 23 '14 at 06:35

user2944170

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Is there combinational circuit design for a 6 operation ALU?

I'm trying to create a ALU in VHDL and I'm having a hard time implementing a couple of the operations. I've implemented the add, subtract, and and or operations but I'm wondering how I would implement the logical shift operations? The ALU is 32 bit…

vhdl alu

asked Feb 03 '14 at 19:22

user2929779

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Visualizing an ALU pipeline when operations have different throughput

How can I visualize an ALU pipeline when operations have different throughput? An ALU pipeline where all operations have the same throughput can be visualized as a factory with a conveyor belt assembly line. The depth and latency of the pipeline…

gpu cpu pipeline alu

asked Feb 02 '14 at 18:35

Roger Dahl

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How ALU execute instruction in AMD GPU (VLIW)?

I wanna ask something about OpenCL programming. I understand that a quarter of wavefront can issue instruction for each cycle clock and it will need four cycle clock to call a wavefront. To finish the instruction in VLIW architecture, it will need…

opencl alu vliw

asked Dec 27 '13 at 02:10

arvin99

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Is it possible to save a calculated value to filesystem without writing it to memory?

Let's say I have two integer variables a and b. I want to sum up a and b and write the calculated result to standard output or a file. Is it possible to do it without writing the result to memory in modern CPU architectures?

memory assembly cpu-registers alu

asked Nov 23 '13 at 00:19

osman

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How ALU actually does if we need to compute power of 2 (say 2 to the power 32) in a 32-bit system,is it possible?

How ALU actually does if we need to compute power of 2 (2ˆ32) in a 32-bit system,is it possible? In simple terms, say I have to compute power with a given base,then if the result of computation is greater than the number of bits that the computer…

processor alu

asked Nov 19 '13 at 09:14

Parveez Ahmed

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Generate Keyword in VHDL

I am trying to create a carry-look-ahead adder/subtractor unit as part of an ALU using VHDL. unlike a conventional adder, this unit must recognize both 32-bit unpacked data and 16-bit packed data and treat them accordingly. So, if I choose to add…

compiler-errors vhdl hdl alu

asked Nov 11 '13 at 05:04

audiFanatic

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test bench multiple architectures

sorry I'm new to this website, but I have been searching for answers for almost 2 days straight. I am new to vhdl, and an assignment has asked to make a simple 16-bit ALU. This ALU needs 2 architectures: the behavioral, as well as the RTL design. I…

vhdl modelsim intel-fpga alu

asked Sep 23 '13 at 19:18

addd45

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Carry/auxiliary flag functions in x86 ALU

I'm trying to create a 8086 processor in Verilog, and I have a better-than-average fundamental understanding of most of the architecture (and can get along happily once I get past this point), but I can't seem to wrap my head around how the Carry…

verilog status x86-16 alu

asked Aug 02 '13 at 18:57

ecfedele

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ALU verilog test bench not sure initialized properly

I'm trying to write the test bench for my ALU but. I'm not sure if its written in a way that makes it work. For instance, should I use dut or uut? Have I initialized my inputs correctly? The output wave is just straight (doesn't change with each…

testing verilog alu

asked May 17 '13 at 19:42

Noha

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8 bit ALU for microprocessor

I have a project where i am supposed to develop a RISC microprocessor . this involves creating an ALU in behavioral model . however there seems to be problems/errors/warnings while simulating the design . most of the operations work properly except…

vhdl processor modelsim alu

asked Apr 18 '13 at 08:59

Abhinav Vishak

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Questions tagged [alu]