Is there combinational circuit design for a 6 operation ALU?

Question

I'm trying to create a ALU in VHDL and I'm having a hard time implementing a couple of the operations. I've implemented the add, subtract, and and or operations but I'm wondering how I would implement the logical shift operations? The ALU is 32 bit but any design would be appreciated.

[so] is focussed on software issues - this is hardware design. Try asking on [electronics.se] — , Feb 03 '14 at 19:26
@MikeW - This could still be ok for SO, given it's about writing an implementation in VHDL. — admdrew, Feb 03 '14 at 19:31
@admdrew Possibly, but the OP is more likely to find someone with the relevant hardware design experience on [electronics.se] — , Feb 03 '14 at 19:34
@MikeW Agreed, and this question isn't very well written to begin with. — admdrew, Feb 03 '14 at 19:35
@MikeW - there's a reasonable number of VHDLers hanging out on SO as well as EE :) — Martin Thompson, Feb 04 '14 at 21:25

score 1 · Accepted Answer · answered Feb 03 '14 at 20:37

The numeric_std package contains logical shift operations, both shift_right and shift_left:

function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
--         The vacated positions are filled with '0'.
--         The COUNT leftmost elements are lost.

function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
--         The vacated positions are filled with '0'.
--         The COUNT rightmost elements are lost.

So based on this you can simply write code like:

library ieee;
use ieee.numeric_std.all;

architecture syn of mdl is
  signal arg   : std_logic_vector(31 downto 0);
  signal count : std_logic_vector( 4 downto 0);
  signal res_r : std_logic_vector(31 downto 0);
  signal res_l : std_logic_vector(31 downto 0);
begin
  res_r <= std_logic_vector(shift_right(unsigned(arg), to_integer(unsigned(count))));
  res_l <= std_logic_vector(shift_left(unsigned(arg), to_integer(unsigned(count))));
end architecture;

These operations are synthesizable, and maps nicely to FPGA resources if that is your target device.

There has previously been some confusion around VHDL shift/rotate operators, see this link, but it has been cleaned up in VHDL-2008. However, for backward compatibility the above suggestion is based on functions instead of operators.

Is there combinational circuit design for a 6 operation ALU?

1 Answers1