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We're doing some work on a CPU in logism in class. We're going over the ALU, and need now need to know different ways multiplication can take place. Our professor gave us two examples, one called the "Five Add Time" and the "31 Add Time" (although I do not believe these are the official names of the algorithm), shown here:

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And Here

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What are the proper names for both these algorithms, and is there any documentation that would allow me to better understand what's going on here? I'd google it, but I am really not sure on the specific term I should look up.

Thanks

Dan
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  • I sure hope your professor continues to more competent multiplier implementations. First one operates on one (`Mplier`) bit-at-a-time, second one uses a tree-like structure. Exercise: why doesn't the second one work? – greybeard Apr 15 '15 at 21:36
  • @greybeard Haha thought someone might say this. This is one of four he gave us, and these two are by far the least competent. Just trying to understand each. – Dan Apr 15 '15 at 21:49
  • @greybeard I am just confused by the diagram because at the top we see "Mplier0* Mcand". I understand taht Mplier0 is bit0 of Mplier, but unsure of what we're supposed to do with that bit against Mcand. – Dan Apr 15 '15 at 21:51
  • `unsure of what […] to do with [bit0 of Mplier] against Mcand` Well, interpret it as a one-bit binary natural number and compute the product with `Mcand` - this just takes 32 "and-gates". But addition in the five-level adder tree might get a bit more tricky than depicted - try to figure out the correct bit positions and required width for the adders, starting with the rightmost one on the second level from top. – greybeard Apr 15 '15 at 22:45
  • booth looks like `Shift and Add` multiplication units. ALUs are used for Adding and the bit shift is hardwired on each ALUs input/output side. 1st. MUL operand is used as ChipSelect signal of each ALU (just single bit from it per ALU) , 2nd. MUL Operand is used as 1st. ADD operand for each ALU and the 2nd. ADD operand is sub-result from previous stage with hardwired shift. The result from ADD is just next sub-result with hardwired bit-shift. Both multipliers do a long binary multiplication The first use serial cascade of adding the sub-results , and the second use Divide and conquer addition – Spektre Apr 16 '15 at 06:19
  • @greybeard There is one gate missing for the bit0 that should be AND of MUL operand1 bit0 and MUL operand2 bit0 ... probably done in previous stage that is not seen on the images – Spektre Apr 16 '15 at 06:23
  • @Spectre: I take it you had a Freudian for `Both look like` (which I find difficult to follow for the second one). Depending on how Boolean logic was introduced, the middle dot in the first line denotes the and-operation (with a some form of `+` for or and a ringed cross for exor?). How wide are the results of the second level of adders, how are they aligned as inputs to the third level? – greybeard Apr 16 '15 at 08:09

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