1 bit ALU whose operations depend on carry in

Question

I have to design a 1 bit ALU for an assignment which would then be reused to make 4 units and a 4 bit ALU.

1 bit ALU has 2 select lines and inputs A, B and a carry in.

My problem is that the select lines AND the carry in flag choose what operation to select. I just have no clue how to use the select lines and carry flag at the same time to select the operation.

For example, select lines "00" and Cin "0" is an add operation whereas Cin "1" is a subtract.

Could I do what I have done below? Thanks for your help.

entity ALU1Bit is
port(
    A:  IN std_logic_vector;
    B:  IN std_logic; 
    carryIn:      IN std_logic;                                  
    operation: IN std_logic_vector(1 downto 0); 

    F:   OUT std_logic;
    carryOut: OUT std_logic
    );
end ALU1Bit;

architecture Behavioral of ALU1Bit is

component Adder1Bit
port(
    carryIn:  IN std_logic;
    A: IN std_logic;
    B: IN std_logic;

    output:  OUT std_logic;
    F: OUT std_logic
    );
end component;

begin
carryIn <= '0';
    case operation is
        when...
carryIn <= '1';
    case operation is
        when...

end Behavioral;

No. Assigning to input ports is an error, for one thing. – Jan 25 '15 at 20:15 — , Jan 25 '15 at 20:15

score 0 · Answer 1 · answered Jan 26 '15 at 11:38

What it looks like you're missing is that you can have nested case statements. Your code:

carryIn <= '0';
    case operation is
        when...
carryIn <= '1';
    case operation is
        when...

Is on sort of the right lines, but a case statement must be within a process, and as Brian says, you're trying to assign '0' and '1' to the carryIn input, which is not allowed. I think what you meant with these two lines was to have them work like another case statement. You want something more like:

process (carryIn, operation, ...)
begin
    case carryIn is
        when '0' =>
            case operation is
                when "00" => ...
                when "01" => ..
            end case;
        when '1' =>
            case operation is =>
            ...
    end case;
end process;

It seems likely that you might have overlapping cases, that is, two or more cases within this structure that actually do the same thing. This is bad because every time you need to change what happens in these cases, you have to change them twice, which is error prone.

In this case you could have one case statement like the one above, that simply assigns an operational mode, using an enumerated type, for example:

type ALU_OP_type is (ADD, SUBTRACT, ...);
signal aluOp : ALU_OP_type;

then in your process:

    case carryIn is
        when '0' =>
            case operation is
                when "00" => aluOp <= ADD;
                when "01" => aluOp <= SUBTRACT;

etc. Then finally another case statement (probably in a separate process) that uses these simple readable operations to do something:

    case aluOp is
        when ADD => ...
        when SUBTRACT => ...

etc. Your code is then well separated into "working out what we're going to do" and "do something". If you don't have duplicate carryIn/operation combinations, then this is probably not worth the effort.

1 bit ALU whose operations depend on carry in

1 Answers1