Why are ALU outputs undefined?

Question

I am designing an ALU in Verilog while I am learning it. I came up with the following code:

Testbench:

module ALUtb;

reg clock = 1'b0;

reg [0:7] val1;
reg [0:7] val2;

initial begin
   val1 = 8'b01010100;
   val2 = 8'b10101000;
   #50 $finish;
 end
 ALU piet(val1, val2,, clock);

always begin
  #5 clock = ~clock
  ;
end
endmodule

 // Main code:

 module ALU(
     a1, a2, out, clock
     );

  output [0:7] out;
  input [0:7] a1;
  input [0:7] a2;
  input clock;

  wire clock;
  reg  out;
  wire co;
  wire a1, a2;

   wire [0:7] poep;

   initial begin
     $monitor("Out=%d, co=%d, a=%d, a2=%d, poep=%d, clock=%d", out, co, a1, a2, poep, clock);
  end

  always @ (posedge clock) begin
     out <= poep;
  end

  adder addy(.output_byte(poep), .co(co), .a1(a1), .a2(a2), .clock(clock));
endmodule 

 module adder(
   output_byte, co, a1, a2, clock
  );
  initial begin
    output_byte = 8'b00000011;
  end
  input [0:7] a1;
  input [0:7] a2;
  input clock;

  output [0:7] output_byte;
  output output_bit;

  output co;

  wire c1;
  reg b1, b2;
  reg [0:7] output_byte;
  wire output_bit;

  integer i;

  always @ (posedge clock) begin
     for(i = 0; i < 8; i = i + 1) begin

      b1 = (a1[i] & (1 << i));
      b2 = (a2[i] & (1 << i));  

      #1 output_byte[i] = output_bit;
  end
  end

 bitadder b_adder(.out(output_bit), .co(), .a1(b1), .a2(b2), .c1(c1));

endmodule

 // Deze module is een 1-bits adder. 
 module bitadder(out, co, a1, a2, c1);

  output out, co;
  input a1, a2, c1;

  wire out, co;

  wire a1;
  wire a2;
  wire c1;

  assign {co, out} = a1 + a2 + c1;

endmodule

In the output, I am getting:

Out=  x, co=z, a= 84, a2=168, poep=  3, clock=0
Out=  3, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  3, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=1
Out=  x, co=z, a= 84, a2=168, poep=  x, clock=0

As you can see, this is only an 8-bit adder. Since even this doesn't work yet, we haven't yet proceeded.

Why isn't the output changing properly? poep is like a buffer for the actual output out. co is the carry-out bit, a is the first number, a2 is the second number, c1 is the carry-in bit, and the rest should speak for itself.

Why are my outputs undefined?

`#1 output_byte[i] = output_bit;` is not synthesizable. You do not even need the `always` block in `adder`, you need 8 `bitadder` linked together — Greg, Nov 30 '16 at 07:37

toolic · Answer 1 · 2023-04-17T13:56:47.240

Your outputs are undefined because you never assigned a value to the c1 signal inside the adder module. You declared c1 as a wire, which defaults to the high-impedance value (z). The problem is that you never drive it with a known value.

Connecting c1 to the input of bitadder results in that module's outputs becoming unknown (x), and that unknown propagates up through the module hierarchy.

The simplest fix is to change:

  wire c1;

to:

  wire c1 = 0;

That clears up the unknown outputs:

Out=x, co=z, a=0, a2=0, poep=  3, clock=0
Out=1, co=z, a=0, a2=0, poep=  3, clock=1
Out=1, co=z, a=0, a2=0, poep=  3, clock=0
Out=1, co=z, a=0, a2=0, poep=  1, clock=0
Out=1, co=z, a=0, a2=0, poep=  0, clock=0
Out=0, co=z, a=0, a2=0, poep=  0, clock=1
Out=0, co=z, a=0, a2=0, poep=  0, clock=0
Out=0, co=z, a=0, a2=0, poep=  0, clock=1
Out=0, co=z, a=0, a2=0, poep=  0, clock=0
Out=0, co=z, a=0, a2=0, poep=  0, clock=1
Out=0, co=z, a=0, a2=0, poep=  0, clock=0
Out=0, co=z, a=0, a2=0, poep=  0, clock=1

My simulators gave me a compile error on the output_byte signal in the adder module. I deleted this line to get rid of the compile error:

  output output_bit;

Why are ALU outputs undefined?

1 Answers1