Input Output for 8-bit ALU using FPGA board

Question

I am a newbie to xilinx so please excuse any stupidities in the code.

Ah so I am trying to design an 8-bit ALU and the module is working perfectly on the simulation but we need to take inputs and display outputs on FPGA board.

Technically I should have used RS-232 but since we just have an 8-bit input and 8 switches are available, we are trying to code it this way.

However, the code does not compile and gives error "expecting 'endmodule', found 'forever'".

I used 'forever' and not 'always' because always does not allow any instance to be instantiated within it.

Can anybody please help us figure out what is wrong with the code?

module main(out,in,switch);
output [7:0] out;
input [7:0] in;
input switch;
reg [7:0] a,b,select;
reg [1:0] count;
wire eq, comp, C8;
initial
begin
count = 2'b00;
select = 8'b0000_0000;
end
MyALU A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);


forever
begin
if (switch)
    begin
        case (count)
        00: 
             begin
             a  = in;
             count = 2'b01;
             end
        01: 
             begin
             b  = in;
             count = 2'b10;
             end     
        10: 
             begin
             select  = in;
             A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);
             count = 2'b00;
             end
        default
             a = in;
      endcase        
    end
end

Loops inside verilog must be inside some procedural block. Use `initial` before `forever`. Or remove `forever` and use `always @(*)` is finer way. `endmodule` is missing here. — sharvil111, Dec 07 '15 at 05:18
Module instantiation is simply outside any procedural block. If multiple instances are required (which is not the case here), use `generate` block. — sharvil111, Dec 07 '15 at 05:22

score 1 · Answer 1 · edited Dec 07 '15 at 17:11

1

Every module in verilog must end with the line endmodule. That is missing in your code. And try using always@(*) instead of forever. forever is not synthesizable and only used for verification with simulation.

edited Dec 07 '15 at 17:11

Greg

18,111
5
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answered Dec 07 '15 at 05:01

Jorc

21
3

score 0 · Answer 2 · edited Dec 08 '15 at 22:45

0

Replace the forever statement by always @(*).
Remove this line from the case statement: A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);
Add endmodule at the end.

edited Dec 08 '15 at 22:45

Kirk Beard

9,569
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answered Dec 08 '15 at 16:28

Anil

1
1

Input Output for 8-bit ALU using FPGA board

2 Answers2