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I'm trying to compile some FPGA code using Xilinx's Vivado tool. However, when I run "Synthesis" and then select "Report methodology"...I get the following list of Bad Practices:


TIMING-17
TIMING #1 Warning The clock pin last_anthony_reg.C is not reached by a timing clock 
TIMING #2 Warning The clock pin last_paul_reg.C is not reached by a timing clock 
TIMING #3 Warning The clock pin last_steven_reg.C is not reached by a timing clock

I'm wondering what is causing this "WARNING" message... I tried looking at the schematic... but it looks ok to me... just see a FDCE and some LUTS, nothing out of the ordinary there.

Here's my VHDL Entity for the FPGA top-level:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example1 is
    port(
        clk           :in    std_logic;
        clear         :in    std_logic;

        richard       :out   std_logic;
        james         :in    std_logic;
        michael       :in    std_logic;
        william       :out   std_logic;       
        david         :out   std_logic;       
        robert        :in    std_logic
    );
end entity;

And the VHDL architecture:

architecture rtl of example1 is
    signal matthew                :std_logic_vector(1 downto 0);
    signal anthony, last_anthony  :std_logic;
    signal steven,  last_steven   :std_logic;
    signal paul,    last_paul     :std_logic;    
begin

process(clk)
begin
    if (rising_edge(clk)) then
        last_anthony <= anthony;
        last_steven  <= steven;
        last_paul    <= paul;
    end if;
end process;

matthew <= (michael and not last_paul) & (robert and not last_steven);

process(
    clear,
    matthew,
    james,    
    last_anthony,
    last_steven,
    last_paul    
)
begin

    if (clear = '1') then
        anthony  <= '0';
        steven   <= '0';
        paul     <= '1';          
    else
        --defaults

        case matthew is

        when "00" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "01" =>
            anthony  <= last_anthony;
            steven   <= last_steven;
            paul     <= last_paul;

        when "10" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "11" =>
            anthony  <= last_anthony;
            steven   <= '0';
            paul     <= '1';

        --synthesis translate_off                
        when others =>
            anthony  <= 'X';
            steven   <= 'X';
            paul     <= 'X';
        --synthesis translate_on

        end case;            
    end if;
end process;

william   <= steven;
david     <= paul;
richard   <= anthony;    

end architecture;
pico
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  • TIMING-17: Non-Clocked Sequential Cell The clock pin is not reached by a timing clock. Description: The DRC reports the list of sequential cells unconstrained by a timing clock which affect the resulting timing analysis for the reported cells. It is highly recommended that all clocks be properly defined in order to get the maximum timing path coverage with the best accuracy. The consequence could be missing timing analysis, which might lead to hardware failures. – pico Aug 14 '19 at 19:52
  • Resolution: The resolution is to create the missing primary or generated clock on the clock tree driving the unconstrained sequential cells – pico Aug 14 '19 at 19:52
  • how to do this? Also, is there a way to do this with vhdl attribute in the code? I thought vivado automatically marks all signals with "clk" in the name as a clock. i'm just not providing the clock period. – pico Aug 14 '19 at 19:52
  • Can't vivado just infer which signal is the clock based on which ever signal is going to "posedge" or "rising_edge" statement? that's what "ISE" used to do when you just run the "synthesis step" without running "implementation step"... – pico Aug 14 '19 at 19:57
  • I'm voting to close this question as off-topic because it belongs on another site in the Stack Exchange network - Electronics. – Matthew Taylor Aug 15 '19 at 07:03
  • It turns out that Vivado has another Level of code linting hidden away that is executed before the the "Synthesis level". It can be accessed under the "flow menu"...goto "Flow->Elaborate Design", then click on "RTL Analysis->Open Elaborated Design->Report Methodology"... this level of "linting" doesn't have any timing rules... – pico Aug 16 '19 at 14:08

1 Answers1

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Can't vivado just infer which signal is the clock based on which ever signal is going to "posedge" or "rising_edge" statement?

Vivado knows what all the clocks are (after all it gives you a warning on your clock pin), but it does not know the parameters of that clock: frequency, duty cycle etc. That is what it complains about: the pin is reached by a clock but not a clock which has timing information: a 'timing clock'.

You have to specify those in the constraints file like:

# define ext pll clock as 100 MHz for timing check
create_clock -period 10.000 -name ext_pll_in [get_ports PL_HP66]

I understand there is a 'Constraints wizard' but I have never used it.
You get to the 'Constraints wizard' option after you have run synthesis and then 'open synthesized design'.

Oldfart
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  • you are probably right... but, in my opinion, Vivado just has some poor coding linting rules that need to be fixed.... Xilinx should just use the list of clocks that were already inferred by synthesizing the code and remove this bogus warning by replace it a real warning message like: "hey, fpga designer dude, you didn't tell us the clock period for this clock, this is going cause trouble when you go to run timing optimization during implementation step"... and then I can say, I don't care... i'm only running synthesis to lint the code and not to setup the timing constraints... – Bimo Aug 15 '19 at 13:40
  • @BillMoore I have to (sigh..) work with Xilinx tools on a daily basis. I have stopped wondering about their weird messages and way of working. Some parts are great others just suck. – Oldfart Aug 15 '19 at 13:51