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Questions tagged [zynq-ultrascale+]

20 questions
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Why are the headers not found in the Xilinx SDK?

I am following the course "Introduction to Deep Learning with Xilinx SoCs Technical Training Course" for the Ultra96v2 board and reached Lab No. 5. I am able to follow along until I am supposed to build the project in the SDK. It fails and tells me…
Vandrey
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1 answer

How to access Xilinx Axi DMA from Linux?

I'm a software developer but I'm a newbie to embedded software development. I have a Zynq Ultrascale board that has an Axi DMA in its Hardware and I want to access this DMA from Linux. I know I should use DMA-Engine to Access DMA in Linux and I…
hamed
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How to find dma_request_chan() failure reason details?

In an external kernel module, using DMA Engine, when calling dma_request_chan() returns an error pointer of value -19, i.e. ENODEV or "No such device". Now, in the active device tree, I do find a dma-names entry with what I'm trying to get a channel…
sktpin
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Silabs Si5340: how to define a clock for one of the chip outputs

We develop hardware that uses Si5340 to provide clocks for various chips (ADC, DAC). Hardware is based on Xilinx Zynq Ultrascale and OS of choice is Petalinux 2018.3. The driver that we use is clk-5341…
matejk
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Value is wrong first time pointer is dereferenced but correct after that

I have a ZYNQ Ultrascale+ MPSoC Genesys ZU dev board that I'm running my application on. I have an accelerator in the PL that is connected to the PS through a simple AXI DMA. The DMA reads the DDR memory through a normal, non-coherent, FPD slave…
Christopher Moore
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How to access XDMA BAR0 in Petalinux?

I have a block design and hardware configuration with a Zynq processor running Petalinux. I furthermore have an XDMA IP configured as a memory-mapped endpoint. I have configured BAR0 and BAR2 in the PCI BARs tab. I am trying to write a simple…
Hedam
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Zynq PetaLinux system PL needs to write to PS RAM - how do I provide PL with the correct physical address?

I have a Zynq system where logic in the PL generates a large block of data that needs to be written into PS RAM. In my naive thinking, I would use new or malloc() to get a pointer to allocated memory, then translate that pointer virtual address to a…
crw4096
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how to simulate JTAG by SPI in zynq

There is some problem in my zynq 7020, and I have to use SPI to simulate JTAG, can someone offer the code to carry out it? please, it's important for me! there's picture that imitate the way that how to make it,but I still don't know how to make…
LuYaHu
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How to access ethernet ports from both RPU and APU?

​ I am using ZU19EG Zynq UltraScale+ MPSoC bought from iWave with APU – Cortex 53 (quadcore) and RPU – Cortex R5 (dualcore). On this board, I am trying to run the sample lwIP echo server application provided in Vitis 2021.1 on RPU in lockstep mode…
Munna
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Cross-Compilation of Point Cloud Library for ARM Cortex R5

I have Zynq UltraScale+ MPSoC board with RPU (Cortex R5). I am trying to create a FreeRTOS application on Cortex R5 to generate point clouds and send it out to a host PC. PCL library has been clonned on my WSL and I am able to compile it. But, when…
Munna
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Zynq Ultrascale (ZU3+) failing SD card init/ident process = "unsupported card inserted"

We have an embedded system that uses a Zynq Ultra Scale (Zu3+) and a microSD card interface. The Zynq project is setup for 3.3V IO using SD 2.0 standards no level shifters. Our manufacturing process uses the SD card to load QSPI and finalize the…
hcalreg
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How to configure UART IO pin multiplexer in u-boot SPL for ZynqMP

Using mainline u-boot (2023.01) I try to configure UART0 I/O pins for the SPL. In the kernel and u-boot proper, this is done via a pinctrl-node in the devicetree. However u-boot 'strips' the devicetree for the SPL and removes the pinctrl node. I…
Waldorf
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What could cause EDAC errors without reporting them, or without actual ECC errors?

I've got a ZynqU+ that I've built and am running embedded linux on. Everything boots fine, and initially runs fine. One problem though is that I see the ue_count in /sys/devices/system/edac/mc/mc0/ is incremented to 13 (ce_count is 0) every time I…
J. Doe
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What is the reason I get this error using bootgen?

I'm creating a .bif file that will run in Vitis. I'm trying to follow the examples from this place: https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded/Creating-Boot-Images This is my create_bif.bat-script that I ran for XSDK that worked perfectly…
Enclustra xu5
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Xilinx Ultrascale UART not found on Big Sur

I'm trying to connect to the serial port of my Xilinx Ultrascale ZCU102 with my Macbook Pro (OS: Big Sur 11.2). The board is connected with a USB - miniUSB cable to a hub USB C connected to one of the Mac USB C ports. With lsusb | grep Serial I get…
Niccolò Borgioli
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