1

i had designed a 32 bit mac unit using VHDL in xilinx . now, i want to calculate the delay theoretically and compare with timing report obtained from xilinx

is there any specific procedure for calculating delay of the logic gate???

Eswar Chandra
  • 11
  • 3
  • 4
    This question belongs on another site in the Stack Exchange network: http://electronics.stackexchange.com/ – Morten Zilmer Feb 17 '16 at 07:03
  • What exactly i the purpose; is it to see how fast that specific implementation could be in the same FPGA device, or how fast it could be in a ASIC implementation thus without the FPGA reprogramming overhead, or other? – Morten Zilmer Feb 17 '16 at 07:08
  • To calculate the delay even as accurately as the Xilinx Static Timing Analyser (STA) would be a massive mount of work. The STA will be calculating the impedance of every section of the every track in the design and then determining what the impact of driving that impedance is on every gate. The STA will be taking into account the rise and fall times of each signal; it might even be taking into account the crosstalk between adjacent tracks. Why would you want to do all that, even it were feasible? – Matthew Taylor Feb 17 '16 at 14:39

0 Answers0