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I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable.

vhdl code:

LIBRARY ieee;
USE ieee.All;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY adder_5 IS
PORT (
 a : IN integer ;
 b : IN integer; 
 c : OUT integer 
);

END adder_5;
ARCHITECTURE add OF adder_5 IS
BEGIN
 c<= (a rem 32) + (b rem 32);
END add;
Cœur
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Sai Rahul
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  • Have searched SO for Verilog and adder? It's full of adder examples.... – Paebbels Apr 16 '16 at 17:51
  • The problem is not about the adder. Its the type of input. I the code to take an integer input which is passed on from another module or block, for example, from a ROM block.@Paebbels – Sai Rahul Apr 16 '16 at 17:58
  • Verilog does not strongly care about types. If I remember correctly integers are for constants and parameters only, not for ports. – Paebbels Apr 16 '16 at 18:23

2 Answers2

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Integers in Verilog and integers in VHDL are not the same thing. In VHDL an integer is a signed 2-state type with at least 32 bits. In Verilog an integer is a 32-bit signed 4-state variable. So, in Verilog,

integer a;

and

reg signed [31:0] a;

are equivalent. In Verilog input ports had to be net types, so integer input ports were not allowed. However, output ports were allowed to be variables, so an output port could be an integer. So, you can replace VHDL input integers with reg signed [31:0] and output integers with integer and your code in Verilog is

module adder (input wire signed [31:0] a, b, output integer c);

  always @(*)
    c = a%32 + b%32;

endmodule

or perhaps for consistancy:

module adder (input wire signed [31:0] a, b, output reg signed [31:0] c);

http://www.edaplayground.com/x/5PZe

So, integers were allowed in output ports but not input ports.

Matthew Taylor
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  • When i compile the code i get the following error: "Port mode is incompatible with declaration: a" @Matthew Taylor – Sai Rahul Apr 17 '16 at 05:34
  • I never heard about IO as an integer!! – Prakash Darji Apr 17 '16 at 07:35
  • @Sai Rahul My appologies - I inadvertently had the SystemVerilog switch enabled, so my code compiled fine. Disabling SystemVerilog caused an error, of course, because input ports cannot be variables. I have modified my answer accordingly. Please let me know how you get on. – Matthew Taylor Apr 17 '16 at 09:24
  • Note that type integer is not designed to be synthesizable so not all synthesis tools will accept it. If you want to make your code synthesizable, you'll need to use `reg signed [31:0]` – Unn Apr 18 '16 at 01:13
  • @Unn It synthesised in DC, Quartus, ISE and Vivado, but if in doubt, you can use `reg signed [31:0]` as you say. – Matthew Taylor Apr 18 '16 at 07:39
0

You can directly use integer with port in Verilog.

Please note that, use integer, and not int in verilog. Because,

int is a 2 state type, having only 2 values 1 & 0. But integer is 4 state type, having 4 values - 0, 1, x, z.

module top (a);
  input integer a;
endmodule
Karan Shah
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