Verilog basic gate data flow not working for NAND & NOR, but works for XNOR & XOR

Question

I have some basic code using data flow statements, but nor and nand functions are not working with this.

module basic_gates_bitwise_df(
input A,
input B,
output andd,orr,nota,nandd,norr,xorr,xnorr
);
assign andd=A&B;
assign orr=A|B;
assign nota=~A;
assign nandd=A~&B;
assign norr=A~|B ;
assign xorr=A^B;
assign xnorr=A~^B;
endmodule

I got errors like this:

ERROR:HDLCompiler:806 - "F:\basic.v" Line 37: Syntax error near "~&".
ERROR:HDLCompiler:806 - "F:\basic.v" Line 38: Syntax error near "~|".
ERROR:HDLCompiler:598 - "F:\basic.v" Line 21: 
Module<basic_gates_bitwise_df> ignored due to previous errors.

What can I try to resolve this?

what are `~&` and others supposed to mean in your case? there are no such operators on two operands in verilog. They can only be used as unary reduction operators. What did you expect? — Serge, Nov 24 '21 at 11:40

toolic · Answer 1 · 2021-11-24T12:44:12.160

Sometimes you get a more helpful message with different simulators. For example, with Synopsys VCS on edaplayground:

Error-[SE] Syntax error
  Following verilog source has syntax error :
    Invalid use of unary operator '~&'
   token is ';'
  assign nandd=A~&B;
                    ^
1 error

To fix the errors, change:

assign nandd=A~&B;
assign norr=A~|B ;

to:

assign nandd=~(A&B);
assign norr=~(A|B);

Refer to IEEE Std 1800-2017, section 11.4.9 Reduction operators :

The unary reduction operators shall perform a bitwise operation on a single operand to produce a single-bit result.

For a NAND, you should AND the 2 inputs, then negate the AND expression.

There is no syntax error with ~^ because it is also a binary operator, as well as a unary operator.

Verilog basic gate data flow not working for NAND & NOR, but works for XNOR & XOR

1 Answers1