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Questions tagged [vivado]

Vivado® Design Suite is a development environment published by Xilinx for designing with their FPGA devices.

The Xilinx Vivado® Design Suite delivers a SoC-strength, IP-centric and system-centric, next generation development environment that has been built from the ground up to address the productivity bottlenecks in system-level integration and implementation. The Vivado Design suite is a Generation Ahead in overall productivity, ease-of-use, and system level integration capabilities.

http://www.xilinx.com/products/design-tools/vivado.html

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Generating sin/cos on Virtex7 with Vivado

I am trying to implement a QAM modulator in SystemVerilog on a Virtex 7 with Xilinx Vivado and I am stuck with the generation of the sin and cos of the local oscillator. More specifically, I have as inputs the I and Q signals (3 bits each) and I…
asonnino
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Why do we have to add a "clr" (clean input wire) while forming a T flip-flop in Verilog with Vivado?

I am trying to form a T flip-flop in Verilog. I am studying verilog from "Digital System Design with FPGA: Implementation using verilog and vhdl" and the code for T flip-flop is here below: module t_flip_flop(t,clk,clr,q,qn); input…
i.just.wacthed.mr.robot
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Logical synthesis of decoder into standard logical cells

I have a decoder defined in verilog as: module my_decoder( input [3:0] in, output reg[19:0] out ); always@(*) begin case (in) 4'd0: out= 20'd114912; 4'd1: out= 20'd114912; 4'd2: out=…
gudise
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Bitstream Encryption

I have a question related to bitstream encryption using eFUSE option. If my FPGA has bitstream encryption key stored in the eFUSE, how Vivado will know the encryption key when generating new encrypted bitstream? Does Vivado has a method to readback…
Tanvir Hossain
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Vivado routing metrics

I'm trying to gather metrics to measure routing utilization on a set of different designs. Any pointers would help a lot! In the Router Utilization Summary, what does "Global Vertical/Horizontal Routing Utilization" measure? Global Vertical…
Alain Zeyu Lou
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Best way to define and initialize matrix in VHDL

I'm trying to make a program that uses matrices( 2d arrays) of integers in vhdl and i have never done that before. First of all, is it possible to define a 2d array in the entity's signal definitions?What I mean is something like this; entity Matrix…
AlexandrosS
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How to fix "Error: Expected expression of type std_ulogic"?

I'm learning VHDL, I tried to implement "adder_array_generic_tree" with two files, the first file "user_defined_type_pkg.vhd" contain: library IEEE; use ieee.numeric_std.all; package user_defined_type_pkg is type signed_vector is array (natural…
Feng Qinping
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iverilog Not Compiling Multiple Port Declarations With Multiple Bits Written In One Line

I am trying to compile Verilog code with a testbench with the last stable version of iverilog 11.0; here is an example: iverilog -o example example.v tb_example.v // example.v module example( input [1:0] input1, [1:0] input2, // problem is…
Celuk
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Concurrent assignment to a non-net '_' is not permitted

I'm getting the error: concurrent assignment to a non-net 'A' is not permitted concurrent assignment to a non-net 'B' is not permitted Static elaboration of top level Verilog design unit(s) in library work failed. What am I doing wrong? module…
qqwetrt8
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Register file not reading any data

I am trying to design a state machine that counts through and replaces values between 47 and 58. In my waveform though, I keep getting XXX for my R_data in the register file, and thus the rest of my top level design is thrown off. I can't seem to…
broncosaurus
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UART Transmit and receive data does not start (Vivado)

I can't figure out why is it that when I set the clock frequency from 50MHz to 100MHz, by changing the clk period to 5 in the testbench, my output transmit and receive data stays at 0. Can anyone enlighten me on this? I need my clock frequency to be…
Coolo
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How to represent 45 degree and 26.565 degree angle in 32 bit binary form?

I am writing the verilog code for CORDIC (COordinate Rotation DIgital Computer) in xilinx vivado. For that I need 45, 26.565 degree rotation angle in 32-bit binary form. After searching in the internet I got 45 degree angle can be represented…
David
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Why shouldn't I be using 'inout' rather than 'in' or 'out'?

I'm relatively new to VHDL and hardware programming and I have a question regarding the port maps and signals. I wanted to read and write to one particular signal in my current project but my lecturer told me I shouldn't use 'inout' but when I asked…
George
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Calling a Module in Verilog

I just started learning hardware programming using Verilog, and I feel lost because I can't understand what errors mean. Here, I am calling the module reg31 module nbit_register(input clk, input [31:0]in, input reset, input L, input load, input…
ProgrammingGuy
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Why can't I use anything but (0 and 1) when I specify the radix in a literal?

y <= a when (s = b"--0") else '0' -- Erroneous. y <= a when (s = "--0") else '0' -- Okay. I'm using Vivado and it gives me the error Error: '-' is not a valid character in b"--0" only if I type the radix in front of the literal. It does the same…
Tortellini Teusday
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