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Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits.

I've included my simulation results. any ideas?

Xilinx Uartlite 2.0 axi4-lite timing simulation

jwanga
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    Did you try waiting for `ready = '1'` before driving `valid` (for all 3 channels). – Jonathan Drolet Jun 06 '15 at 17:31
  • I was under the impression that one drives valid signals first when the input is ready then the module returns a ready signal. That seems to be the flow according to this AXI4-lite doc: http://www.silica.com/fileadmin/02_Products/Productdetails/Xilinx/designing_a_custom_axi_slave_rev1.pdf – jwanga Jun 06 '15 at 18:06
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    Theoretically yes, but I've had problem in the past with some Xilinx IP. If you do not drive valid, does ready rises? – Jonathan Drolet Jun 06 '15 at 18:07
  • Unfortunately not. If I don't drive valid, ready stays low – jwanga Jun 06 '15 at 18:13
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    Other pointers would be to not release reset until valid is stable. Right now reset is released while valid is 'U' or 'X'. Also, AXI has an active-low reset, do invert your reset and do not show it in your simulation? – Jonathan Drolet Jun 06 '15 at 18:15
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    Few ideas: (1) get rid of 'X' by "initializing" your testbench signals (just to make it neater); (2) @JonathanDrolet gave you a supreme hint about reset; (3) paste a snippet of how are you driving signals. – delirium Jun 08 '15 at 14:26
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    I had a recent experience with another xilinx IP core where if any of the inputs were 'X' when it came out of reset, it would never recover and just output zeros for the entire simulation. As other people already mentioned I would make sure everything is initialized and that you're coming out of reset in the correct sequence. – Bob Jun 09 '15 at 12:21
  • Thanks every one. I got it working! I had to invert the reset and ensure all the inputs were initialized. @ JonathanDrolet. Mind posting you comment in the form of an answer so i can give you credit? – jwanga Jun 11 '15 at 06:30
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    Your VALID logic **must not** depend on READY. It's in the AXI Standard, which I recommend you read. READY is allowed to wait for VALID, not the other way around. Once you're VALID, you have to stay valid until the handshare is complete, i.e. READY is asserted. So your core probably behaves correctly and your master behaves incorrectly. Also, your simulation shows a **high-active** RESET, while AXI_ARESET_N is **low-active**. Make sure this isn't the source of your problems. – FRob Jun 11 '15 at 16:48

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For posterity, Had to invert the reset and ensure all the inputs were initialized. Thank you for the helpful comments. I've attached a working simulationenter image description here

jwanga
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  • Hi! I don't really understand what happened here. I thought you wanted to get the ready signals high? In the waveform you posted, none of the ready signals are high. – jodumagpi Apr 26 '22 at 09:20