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Using Vivado 2015.1, I'm attempting to use a hierarchical name to access an object on the top level module of my design. The simulation runs fine but I receive the following synthesis error:

[Synth 8-660] unable to resolve 'top' ["child.sv":3]

module top()
    logic foo;
endmodule

module child()
    always(bar) begin
        logic top.foo <= bar;
    end
endmodule

Any Ideas?

jwanga
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  • With Verilog you are trying to describe hardware. The language in part revolves around describing connectivity between modules. How you are describing the logic it would be very hard to know if `foo` had multiple drivers. As the design got more complex coding like this will eventually start to be unmaintainable. Unable to know what is setting the foo value. – Morgan Jun 25 '15 at 11:44
  • My attempted solution is not ideal, however, the code I posted is just a trivialized example. In my actual implementation, "foo" is so large that it alone is the primary memory constraint of my design. If I were to pass foo to a lower module via a port then a copy would be made, this will quickly max out my chip as I add sub modules. Can you suggest a better strategy for manipulating a reg in a parent module from a child module without making copies? Thanks. – jwanga Jun 25 '15 at 16:38
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    "A copy will be made", I do not understand this, A copy to where? A wired connection will be made, not copied. – Morgan Jun 25 '15 at 17:52
  • The code is just wrong, you can't access an upper module (see it as scope). You can go top to bottom, parent to child but you can't access the parent from the child. It's like any other language, when `child` is compiled, it doesn't know `top`. Verilog files are compiled one by one and must be compiled in order. (Vivado reorder them for you when you open the project, Modelsim doesn't) – Alexis Dec 16 '21 at 22:51

2 Answers2

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So, It turns out that hierarchical names are not supported in Vivado synthesis.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug901-vivado-synthesis.pdf

jwanga
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    Hierarchical referencing should only be used for test-bench. The SystemVerilog and Verilog languages are for design and verification. If hierarchical referencing was synthesizable, there would be no point to have input/output/interface ports. – Greg Jun 29 '15 at 15:52
  • sometimes and it's easier to just use hierarchical names, I use them very often before modifying all the top modules. Supported in vivado 2019.1 – Alexis Apr 09 '20 at 03:35
1

Supported in Vivado 2019.1 UG901 enter image description here

Alexis
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  • The table still doesn't tell if the support is for synthesis or only for simulation. But I'll take your word for it. – andrsmllr Jul 16 '20 at 08:16
  • This table is for Verilog synthesis, and the hierarchical names feature is supported since Vivado 2017.3. – Tey' Jan 27 '21 at 14:59
  • referencing Top inside a submodule doesn't work for me in Vivado 2021 – LiamSnow Dec 16 '21 at 18:20
  • of course, it doesn't make sense... hierarchical goes only top to bottom, parent to child. It can't go up. – Alexis Dec 16 '21 at 22:50