VHDL: formal port 'portName' has no actual or default value

Question

I receive a compilation error on VHDL test bench instantiating VHDL module PWM: "formal port 'Duty_Cycle' has no actual or default value". The error is seen when standing on "dev_to_test: PWM" line of code. In instantiated PWM module the Duty_Cycle stg_logic_vector is casted to unsigned and then is assigned to integer but don't think this may influence the port instantiation. I tried to pass the "00001111" vector value in the port map, which results in the same error. Please, help determine what the error is.

architecture test of test_pwm is
component PWM
    Generic (
        BIT_DEPTH   : integer;
        INPUT_CLK   : integer; -- 50MHz
        FREQ        : integer); -- 50Hz
    Port (
        Pwm_Out     : out std_logic;
        Duty_Cycle  : in std_logic_vector(BIT_DEPTH - 1 downto 0);
        Clk         : in std_logic;
        Enable      : in std_logic);
end component;

constant BIT_DEPTH  : integer := 8;
constant INPUT_CLK  : integer := 125000000; -- 50MHz
constant FREQ       : integer := 50; -- 50Hz

signal Enable      : std_logic := '0';
signal Duty_Cycle  : std_logic_vector(BIT_DEPTH - 1 downto 0) := "00001111";
signal Clk         : std_logic := '1';
signal Pwm_Out     : std_logic;   


begin
    dev_to_test: PWM
        generic map(BIT_DEPTH,INPUT_CLK,FREQ);
        port map(Pwm_Out,Duty_Cycle,Clk,Enable);

A simple typographic error as shown by Giampietro Seu can be detected by providing a [mcve] and trying (here analyzing or 'compiling') that example. This is a syntax error with the extraneous semicolon that should have yielded an error to the effect `port` doesn't lead to a concurrent statement. The error is caused by the component instantiation statement being comprised of required elements (the label, the component name) and two optional elements (generic map and port map aspects) which are integral and not concurrent statements. — , Aug 24 '19 at 16:50
IEEE Std 1076-2008 11.7.1 "A component instantiation statement and a corresponding configuration specification, if any, taken together, imply that the block hierarchy within the design entity containing the component instantiation is to be extended with a unique copy of the block defined by another design entity. The generic map and port map aspects in the component instantiation statement and in the binding indication of the configuration specification identify the connections that are to be made in order to accomplish the extension." — , Aug 24 '19 at 23:11
3.1 "A design entity may be described in terms of a hierarchy of *blocks*, each of which represents a portion of the whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an *external* block that resides in a library and may be used as a component of other designs. Nested blocks in the hierarchy are *internal* blocks, defined by block statements (see 11.2)." Blocks not modules. What version of Vivado? In synthesis internal block statements can't have port or generic clauses while they simulate just fine. — , Aug 24 '19 at 23:22

Giampietro Seu · Accepted Answer · 2019-08-24T16:28:26.490

IEEE Std 1076-2008

11.7 Component instantiation statements

component_instantiation_statement ::=
    instantiation_label :
        instantiated_unit
            [ generic_map_aspect ]
            [ port_map_aspect ] ;

and

generic_map_aspect ::=     
   generic map (generic_association_list )

You have a semicolon too much at the end of generic map(BIT_DEPTH,INPUT_CLK,FREQ);, for this reason, it is not seeing the mapping of the ports and giving you the error. To solve the error just delete that semicolon:

dev_to_test: PWM
        generic map(BIT_DEPTH,INPUT_CLK,FREQ)
        port map(Pwm_Out,Duty_Cycle,Clk,Enable);

PS: to reduce the risk of design errors, it is good practice to use named association in port and generic mapping instead of positional.

I just wanted to comment that I got this error due to another semicolon problem. I separated the items in my port map with semicolons instead of commas. — James, Mar 15 '23 at 20:47

VHDL: formal port 'portName' has no actual or default value

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