Questions tagged [verilog]

For use with the Verilog hardware-description language. Also tag with the IDE or fpga used, if applicable.

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction.

Logic synthesis

Automated tools are able to translate Verilog code meeting certain restrictions into a gate-level description of the circuit that can then be implemented in an FPGA or IC. The task is in some ways similar to the task of a compiler for conventional programming languages, but such tools for Verilog are known as "synthesis tools". Language constructs and coding styles that can be processed by synthesis tools are known as "synthesizable". Constructs that are not synthesizable may be used for testbenches, reference models, or debug instrumentation.

When asking a question, please specify whether you are looking for a synthesizable solution.

Sometimes referred to as Verilog HDL, not to be confused with VHDL.

Standardization

Verilog was initially a proprietary system developed by Gateway Design Automation (later acquired by Cadence Design Systems). Verilog became an open standard under the auspices of Open Verilog International (OVI). OVI became part of Accellera, a non-profit organization that develops standards for modeling and verifying system-level designs. Accellera contributes standards to the IEEE once they are mature, and Verilog became standardized as IEEE 1364. The last version was IEEE 1364-2005 (not available as a free download). IEEE 1364 Verilog has been superseded by IEEE 1800 SystemVerilog.

Tags specific to Verilog

system-verilog system-verilog-assertions system-verilog-dpi uvm vpi icarus iverilog verilator

6035 questions

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1 answer

Is $readmem synthesizable in Verilog?

I am trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its program. If I use $readmemb, will that be correctly synthesized to a ROM? If not, what is the standard way to do this?

verilog synthesis

asked Dec 01 '10 at 04:00

user526035

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3 answers

Is there a simple example of how to generate verilog from Chisel3 module?

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog. I take Gcd source code given on official web page of chisel. import chisel3._ class GCD extends Module { val io = IO(new Bundle { val a =…

scala sbt verilog chisel

asked Nov 07 '16 at 16:39

FabienM

3,421
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45

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3 answers

Error "procedural assignment to a non-register result is not permitted"

I'm getting the error [Synth 8-2576] procedural assignment to a non-register result is not permitted ["lpm_mult.v":29] What am i doing wrong? module lpm_mult ( dataa, datab, // multiplicand,multiplier sum, // partial…

verilog vivado

asked Jul 17 '15 at 09:27

Helyx

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1 answer

Unnecessary spaces in Verilog Display

I'm trying to display some 32 bit values in decimal, and this is working fine other than the strange amount of unecessary spaces between my %b and the previous character. for example: if i have a 32-bit reg a with a decimal value of 33, i'll use…

verilog spaces

asked Jul 12 '15 at 09:36

Jay

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1 answer

Passing parameters to Verilog modules

I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different…

module verilog system-verilog fpga parameterization

asked Dec 18 '14 at 20:38

eavsteen

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1 answer

Accessing local module variables from test benches in Verilog

When writing a Verilog test bench to verify a module is there any way to access a particular variable local to that module from the test bench?

verilog

asked Nov 02 '13 at 01:57

Krish

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7 answers

Resources for learning Verilog

I'm new to Verilog. Can someone suggest a learning resource, book, video, blog or anything that they had a good personal experience with and helped them learn it faster? If it helps, I have experience programming in several high-level languages,…

microcontroller verilog fpga

asked Dec 21 '09 at 04:04

harry

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3 answers

Program to create a Verilog block diagram

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what algorithms I need to look into? I found a good Verilog parser, but now I need to find the relation between each block and place them…

algorithm verilog register-transfer-level

asked Jul 30 '13 at 20:36

user591124

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2 answers

What is the difference between single (&) and double (&&) ampersand binary operators?

In IEEE 1800-2005 or later, what is the difference between & and && binary operators? Are they equivalent? I noticed that these coverpoint definitions behave identically where a and b are of type bit: cp: coverpoint a & b; cp: coverpoint a && b;

verilog system-verilog

asked Jun 26 '13 at 18:23

Victor Lyuboslavsky

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1 answer

Floating Point Divider Hardware Implementation Details

I am trying to implement a 32-bit floating point hardware divider in hardware and I am wondering if I can get any suggestions as to some tradeoffs between different algorithms? My floating point unit currently suppports multiplication and…

algorithm math floating-point hardware verilog

asked Jun 13 '13 at 23:05

Veridian

3,531
12
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3 answers

How to design a 64 x 64 bit array multiplier in Verilog?

I know how to design a 4x4 array multiplier , but if I follow the same logic , the coding becomes tedious. 4 x 4 - 16 partial products 64 x 64 - 4096 partial products. Along with 8 full adders and 4 half adders, How many full adders and half…

verilog multiplication

asked May 23 '13 at 07:45

chitranna

1,579
6
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4 answers

How do I read an environment variable in Verilog/System Verilog?

How do I read an environment variable in Verilog ? (Running on a VCS simulator) I am trying to accomplish File=$fopen("$PATH/FileName","r"); $PATH is an environment variable.

environment-variables verilog system-verilog

asked Feb 22 '13 at 22:08

Jean

21,665
24
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119

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2 answers

What is the meaning of the hex value syntax with an underscore? eg:parameter FOO = 20'h0002_0

Pretty much just the title. What does that underscore mean? How is this different from: parameter FOO = 20'h00020; I don't know what to look for to find an answer to this question as I don't know what this type of syntax is called.

parameters syntax verilog system-verilog

asked Sep 11 '12 at 20:40

supernun

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2 answers

" is not a constant" error in if-statement

I am trying to write a simple module to output a 14-bit number based on the value of four input signals. My attempt is shown below. module select_size( input a, input b, input c, input d, output [13:0] size ); if (a) begin …

verilog

asked Aug 06 '12 at 21:43

tomocafe

1,425
4
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35

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1 answer

How to set up Eclipse for FPGA design in VHDL and Verilog)?

I am new with Eclipse, I have used it for SW development and in Altra environment for Nios processor. But now, I have a pretty large project that I have to manage and I would like to use Eclipse to have all the files in the system to make it easier…

eclipse eclipse-plugin vhdl verilog fpga

asked Jun 28 '12 at 07:12

FarhadA

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