What is the difference between structural Verilog and behavioural Verilog?

Question

As in the title, what are the main differences between structural and behavioural Verilog?

Answer 1

There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.

Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells.

Answer 2

Structural

Here functions are defined using basic components such as an invertor, a MUX, a adder, a decoder, basic digital logic gates etc.. It is just like connecting and arranging different parts of circuits available to implement a function.

Behavorial

The Behavioral description in Verilog is used to describe the function of a design in an algorithmic manner. Behavioral modeling in Verilog uses constructs similar to C language constructs. Further , this is divided into 2 sub categories .

• (a) Continuous

assignment of data to outputs are continuous. This will be implemented using explicit "assign" statements or by assigning a value to a wire during its declaration . In case of assign any change in input will immediately effect the output . Hence output is to be declared as wire

• (b) Procedural

Here the data assignments are not carried out continuously instead it happens on specific events specified in sensitivity list. This type of modelling scheme is implemented using procedural blocks such as "always"or "initial" .

Here, output variables must be defined as reg because they need to keep hold of previous value until new assignment occurs after any change in specified sensitivity list.

Hope this helps :)

Answer 3

Structural Verilog is usually referred to a Verilog code which is synthesizable (has an accurate and meaningful hardware realization) and is usually written in Register Transfer Level (RTL). On the other hand Behavioral Verilog is usually a behavioral description of a hardware or functionality on a higher level. behavioral code does not have to be synthesizable for example when you define a delay in your verilog code scaled by the timescale, the synthesizer does not consider it when it is translating your code into logic and hardware, but rather it has simulation purposes. The same goes for structural and behavioral VHDL.

Answer 4

Behavioral doesn't use logic gates description you can use And,Or,Not gates that are already defined in verilog while structural uses logic gates description where you describe that you want a module called (And/Or/Not) and describe what it does & / | / ~.

Answer 5

Structural verilog deals with the primitives in simple word like and, or, not etc.. The primitives are called/inferred from libraries and connected with input output ports. Example

 module structural(y,a,b);
    input a,b;
    output y;
    and a1 (y,a,b); // and is the primitive inferred and a1 is the instance name.
 endmodule

Behavioral verilog deals with the logic or behavior of a system. It handles complex logic implementation and which is why in industry all implement the behavioral models of the system called as RTL. Once the behavioral RTL is validated by front end engineers using SV/UVM then this RTL is converted into Gate Level i.e Structural which go for synthesis.

Please refer the book of verilog written by Samir Palnitkar for more details.

Answer 6

Verilog is both a behavioral and a structural language. Internals of each module can be defined at four levels of abstraction, depending on the needs of the design. Structural Verilog describes how a module is composed of simpler modules or of basic primitives such as gates or transistors. Behavioral Verilog describes how the outputs are computed as functions of the inputs.

Behavioral level
->This is the highest level of abstraction provided by Verilog HDL. mainly construct using "always" and "initial" block.

Dataflow level
-> At this level, the module is designed by specifying the data flow. condition describe using "assign" keyword.

Gate level
->The module is implemented in terms of logic gates and interconnections between these gates.

Switch level
->This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them.