I'm a beginner in design verification. I wonder why the code below is used in almost every class.
class uvm_test_top extends uvm_test;
`uvm_component_utils(uvm_test_top)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction // ?
I want to know what the new function is from the parent class.
The new function is a member of every class in SystemVerilog. Refer to IEEE Std 1800-2017, section 8.4 Objects (class instance)
A class defines a data type. An object is an instance of that class. An object is used by first declaring a variable of that class type (that holds an object handle) and then creating an object of that class (using the new function) and assigning it to the variable.
UVM, which is a library of classes, has the uvm_test class which is described in the UVM class documentation, under the COMPONENTS category. From the class hierarchy, you can see this class is extended from the uvm_object class, and all classes so extended must declare the new function.
Nearly all UVM classes are extended from uvm_object. This class constructor has a string name argument which is used for messaging and debugging.
uvm_test extends from uvm_component which extends from uvm_object. The constructor of uvm_component adds a uvm_component parent argument which is used to create the testbench hierarchy. The testbench hierarchy encapsulates reusable pieces of the testbench as well as selectively applying configuration and report settings.
