Let's say I have a fixed point value in my VHDL - Code which is defined as std_logic_vector. I know that my last 4-bit are the decimals.
When I use the simulator it will of course not see the last 4 bits as decimals, is there any possibility to change it in the simulation, so that the simulation knows that the 3rd bit has the value of 0.5 , the 2nd the value of 0.25 and so on ?
It's possible in Vivado to show the result in the simulator as a fixed point representation.
When you rightclick in the simulator on the signal you want to show in fixed point, click radix --> real settings. There you get the following window and you can select fixed point.
I doubt about that this is possible unfortunately. Specifically for std_logic the types are the following:
'U': Uninitialized. This signal hasn't been set yet.
'X': Unknown Impossible to determine this value/result.
'0': Logic 0
'1': Logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0 'H': Weak signal that should probably go to 1
'-': Don't care.
As a result the simulator is recognizing ONLY the above symbols, anything else will result in error, including a floating point number to describe a bit. Here's an example from me trying to put a floating point value to be displayed:
add_force {/test/a[27]} -radix unsigned {0.4 0ns}
ERROR: [Simtcl 6-179] Couldn't add force for the following reason: Illegal value '0.4': Could not convert value '0.4' to a decimal number.
I also observed Vivado as tagged so I guess you use the integrated simulator. In my example the closest to a floating point number was the decimal number. There is no built in variable at Vivado to support floating points for display in the simulation. Below you see the radix it supports so you are tightly restricted only to those choices, which all result in error except ASCII but I don't think that's the behavior you want.
