I am trying simulate a SystemVerilog code for an N-bit full adder, but I am getting this error:
Error (10161): Verilog HDL error at full_adder_tb.sv(73): object "std" is not declared. Verify the object name is correct. If the name is correct, declare the object.
Why is it saying "std" is not declared? I used quartus prime software to simulate the code.
Here is my code for testbench.
module full_adder_tb;
timeunit 1ns;
timeprecision 1ps;
localparam N = 8 ;
logic signed[N-1:0] A,B,S;
logic ci,co;
N_bit_adder #(.N(N)) dut(.*);
initial begin
A = 8'd80 ;
B = 8'd12 ;
#1 assert({co,S}==A+B+ci)
$display("OK");
else $error("Not OK");
repeat(10) begin
#9
std::randomize(ci);
#1
assert({co,S} == A+B+ci) $display("OK");
else $error("Error occurred");
end
end
endmodule
Does anyone know a solution for this?
I searched in different websites, but there is no error in the code seems to be. But, it is giving a error message "std" is not declared.