Generation of up/down counter waveform

Question

I tried to generate a waveform for a 4-bit up/down counter in modelsim; my code got compiled, but it is stuck to zero not getting the values based on the values of up_down.

module up_down_counter(clock, din, load, up_down, resetn, count);
   input clock;
   input [3:0]din;
   input resetn, up_down, load;
   output [3:0]count;
   reg [3:0]count;
   always@(posedge clock)
     begin
          if(resetn == 1'b1)
                begin
                    count <= 4'b0;
                end
          else if(load == 1'b1)
               begin
                    count <= din;
               end
          else if(up_down == 1'b1)
               begin
                    count <= count + 1;
               end
          else if(up_down == 1'b0)
               begin
                   count <= count - 1;
              end
      end
endmodule

//testbench

 module up_down_test;
   reg clock;
   reg [3:0]din;
   reg resetn, up_down, load;
   wire [3:0]count;
 
up_down_counter DUV(clock, din, load, up_down, resetn, count);

       always #8 clock = ~clock;

   initial
       begin
            clock = 1'b0;
            resetn = 1'b0;
            load = 1'b1;
            up_down = 1'b0;
            din = 4'b0000;
            #200 $finish;
        end

          always #80 up_down = ~up_down;

    initial
          $monitor("%d/n",count);
endmodule 

These are my codes: one is RTL and another one is a testbench.

Answer 1

Your count is stuck at 0 because you load the counter with din (which is 0) on every clock cycle because you always drive load = 1 in the testbench. You need to set load to 0 after some time.

You should drive your inputs (after time 0) using nonblocking assignments (=>) and at the posedge of the clock. Here is one way:

   initial
       begin
            clock   = 0;
            resetn  = 0;
            load    = 1;
            up_down = 0;
            din     = 4'b0000;
            repeat (2) @(posedge clock);
            load <= 0;
            repeat (20) @(posedge clock);
            $finish;
        end

        always begin
            repeat (10) @(posedge clock);
            up_down <= ~up_down;
        end