SystemVerilog passing functions as an argument

Question

Is it possible to pass a function as an argument in SystemVerilog?

This code hopefully demonstrates though it doesn't work. Any help? Thanks.

    module funcparam;
            int result;

            function int xxx(int x, ref fun);
                    return fun(x);
            endfunction

            function int yyy(int y);
                    return y * (y + y);
            endfunction

            initial begin
                    result = xxx(5, yyy);
                    $display("result: %d", result);
            end
    endmodule

it seems that there is really no support for the language. – e19293001 Dec 14 '12 at 06:26 — e19293001, Dec 14 '12 at 06:26
Unbelievable we still don't have this. – Nimrod Weinberg Jul 26 '23 at 14:01 — Nimrod Weinberg, Jul 26 '23 at 14:01

score 6 · Accepted Answer · answered Dec 12 '12 at 16:10

You're limited as to what can be passed by reference:

a variable,

a class property,

a member of an unpacked structure, or

an element of an unpacked array.

You might be able to pass in a handle of a base class, though I doubt this would work.

class base;
  function yyy(int x);
  endfunction
endclass

class class1 extends base;
  function yyy(int x);
  endfunction
endclass

class class2 extends base;
  function yyy(int x);
  endfunction
endclass


module funcparam;
   result;

   function int xxx(int x,input base fun);
     return fun.yyy(x);
   endfunction

   class1 cls = new;
   //class2 cls = new;


    initial begin
       result = xxx(5, cls);
      $display("result: %d", result);
    end
endmodule

score 4 · Answer 2 · answered Dec 11 '12 at 17:14

4

No.

Tasks and functions can only accept data types as arguments, and functions are not data types. Also there is no way to make a function into a data type.

answered Dec 11 '12 at 17:14

dwikle

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SystemVerilog passing functions as an argument

2 Answers2