Is the ++ operator in System Verilog blocking or non-blocking?

Question

Good coding convention says that we should use blocking assignments in a combinational block, and non-blocking assignments in a sequential block. I want to use the ++ operator in a combinatorial block, but I don't know if it is blocking. So is this code:

input [3:0] some_bus;
logic [2:0] count_ones;
always_comb begin
  count_ones = '0;
  for(int i=0; i<4; i++) begin
    if(some_bus[i])
      count_ones++;
  end
end

equivalent to this:

input [3:0] some_bus;
logic [2:0] count_ones;
always_comb begin
  count_ones = '0;
  for(int i=0; i<4; i++) begin
    if(some_bus[i])
      count_ones = count_ones + 1;
  end
end

or this:

input [3:0] some_bus;
logic [2:0] count_ones;
always_comb begin
  count_ones = '0;
  for(int i=0; i<4; i++) begin
    if(some_bus[i])
      count_ones <= count_ones + 1;
  end
end

I did look in the 1800-2012 standard but could not figure it out. An answer that points me to the appropriate section in the standard would be appreciated.

score 18 · Accepted Answer · edited Mar 19 '14 at 15:55

18

According to section 11.4.2 of IEEE Std 1800-2012, it is blocking.

SystemVerilog includes the C increment and decrement assignment operators ++i , --i , i++ , and i-- . These do not need parentheses when used in expressions. These increment and decrement assignment operators behave as blocking assignments.

edited Mar 19 '14 at 15:55

Greg

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answered Mar 19 '14 at 14:54

dwikle

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So is there a non-blocking equivalent to ++ or do we have to verbosely code:count_ones <= count_ones + 1; – WestHamster Jan 21 '20 at 13:09
@WestHamster I believe that is correct. `val <= val+ 1;` will occur on the event. At least, it is also well supported even if some standard does all an alternate in future. – artless noise Sep 23 '22 at 18:18

Is the ++ operator in System Verilog blocking or non-blocking?

1 Answers1