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Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

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Difference in initializing a state machine between a simulator and synthesizer

My question is regarding the first state used in a synthesized state machine. I'm working with a Lattice iCE40 FPGA, the EDA Playground for simulation and Lattice's Diamond Programmer for synthesizing. In the following example I am generating a…
Ron
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Turning on VHDL standard 2008 for Synopsys dc_shell analyzer

I get trouble to get my code that is a correct VHDL (2008 release of language) code correctly analyzed by dc_shell. The case structure below that is valid 2008 generates an error gen1: case myInt generate when 0 => ... when 1 => …
Clement
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What is the difference in defining a variable in .h file's interface() method alone without synthesizing it?

I define a variable in .h file's interface method like this... @interface ......{ int a; } Then i use it in .m file, it works fine.... Also i modified the code as @interface ......{ int a; } @property(nonatomic) int a; in .h file, and in .m…
Rajkanth
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Why is this not synthesizable? (does not hold its value under NOT(clock-edge))

I'm a software engineer (JAVA/C++) and not an electrical engineer so you can imagine that VHDL is thoroughly confusing to me because I have little idea what the synthesizer is trying to do behind the scenes. And it's telling me it can't synthesize…
WiegleyJ
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Verilog strange simulation results post synthesis

I am facing a strange problem. The code is for a simple ALU. Only code of interest is pasted here: always @(posedge clk or posedge rst) begin if (rst == 1) begin mul_valid_shr = 3'b000; end else begin if…
Qazi
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Basic sound generation/synthesis library, any language

I'm writing a small web app for a music psychology project that will play a series of sound samples for a subject and ask them to rate each one. I need to generate a series of tones (probably all sine waves) with one or two basic filters/effects…
Alex
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Verilog: Does Vivado Synthesis tool, add signals to sensitivity list automatically?

module Test( input i ); (* MARK_DEBUG = "TRUE" *) reg b; always @(i) begin if(i) b = 1'h0; else b = ~b; end endmodule After synthesizing this code I get the following result during Post-Synthesis-Simulation…
manili
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How to add a hand-layout custom circuit as a new std cell and refer to it in verilog?

We have a critical circuit at the heart of our implementation, which is the speed limiter for the entire design. It consists of just a couple dozen gates. We have implemented a custom transistor level circuit for this function by hand, done a…
seanhalle
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Does the Synthesis of unused signals waste hardware resources?

I am working on fixing a broken project. One of the things which I came across in the process was that there where many declared but never used signals, which led me to this question! Would the synthesiser waste hardware resources by implementing…
Aboudi
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Verilog code will simulate but won't synthesize.

This is the code for my finite state machine // `timescale 1ns / 1ps //Moore Finite State Machine Lab 3 // // WORKING, needs Screen output module moore( input BTNC, //manual clk input SW0, //clr input SW1, input SW2, …
c g
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Nyquist Frequency Restriction - How to only mix harmonics that are below the Nyqvist Limit

I am using the getSampleRate() helper function to work out the Nyquist limit and assign it to a temporary local variable. I must now update the part of the class that mixes the harmonics together so that only harmonics with frequencies below the…
Neo
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VHDL syn_looplimit and synthesis

I have a problem in synthesis with my VHDL code : I am trying to get the logarithm value of an input signal S_ink: My code : entity .... .... architecture rtl of myEntity is attribute syn_looplimit : integer; attribute syn_looplimit of loopabc :…
lctdim
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D-flip flop with 2 reset: synthesis error

I'm doing a synthesis of a digital block and I need a D-Flip-Flop with 2 asynchronous resets. The reason is that I will drive one reset with an available clock, and I will use the second one to reset all the registers of my digital block. I…
clidre vandijk
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Indexed part select synthesizable in verilog

Can I use something like code below (counter value in vector index) in my verilog code? data_out[cnt*32 + 31 : cnt*32] = data_in; Is this construct synthesizable in xst? I've got a constant defined data_out range and cnt is incremented on clock and…
user2921643
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How is /= translated to actual hardware in vhdl

I am a beginner in VHDL/FPGA programming. I want to compare two 32-bit std_logic_vectors. I am currently using: if ( RX_FRAME(to_integer(s_data_counter)).Data /= REF_FRAME(to_integer(s_data_counter)).Data ) then s_bad_frame <= '1'; …
Vinay Madapura
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