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Questions tagged [synthesis]

Synthesis turns a high level circuit description into an implementation in logic gates.

Synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) described in VHDL or Verilog, is turned into a design implementation in terms of logic gates.

Wikipedia

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Synopsys design compiler- view datapath extraction results

I am using Synopsys Design Compiler(SDC) for synthesis with compile_ultra. This option does advanced datapath extraction which basically tries to group(or chain) together as many arithmetic operations as possible and then uses carry-save arithmetic…
shrm
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Is it normal for this combinational code to generate latches?

I am doing some investigation on what kind of code does/does not generate latches on different synthesizers. The code below drives a 7-segment display from a 4-bit input. I would expect it not to generate latches, because all possible cases are…
VHDL Addict
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VHDL: The following files are missing: .stx, .ncd, .xrpt

Before I even start with synthesis(as soon as I press "Save"), I get this warnings: WARNING:ProjectMgmt - File C:/Users/bojanm/Desktop/Enkoder-Digital Output/Test/Counter.stx is missing. WARNING:ProjectMgmt - File…
Бојан Матовски
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XCode 4.5 auto generation of @synthesize

I understand that in xcode 4.5 it auto generates @synthesize and also implements the underscore prefix best practice to the variable assignment (as mentioned in another thread). I have TWO related question which your help will be greatly…
MoMo
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Can Flash do low-latency audio synthesis?

When synthesising sound using the SAMPLE_DATA event of the Sound class, the Flash documentation recommends writing out as many samples as possoible up to 8192. On my system the sound cuts out unless I write at least 4192 samples each event. That's a…
user1300292
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iOS sine wave generation - audible clicking

I am in the process of creating a synthesiser for iOS. After playing around and attempting to learn core audio, I have encountered a problem that I cannot get my head around. My sine wave makes a clicking noise on regular intervals, which Im…
Mordapps
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Logical synthesis of decoder into standard logical cells

I have a decoder defined in verilog as: module my_decoder( input [3:0] in, output reg[19:0] out ); always@(*) begin case (in) 4'd0: out= 20'd114912; 4'd1: out= 20'd114912; 4'd2: out=…
gudise
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Why Yosys synthesis the sequential statement to constant

I have the Verilog statement below: module test (A,B, CLK); input A, CLK; output B; always@(posedge CLK) if(A) B <= 1'b1; endmodule I am expecting a register. However, after I synthesis it with Yosys, I got the result as…
Donghui Li
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Simultaneously generate multiple sine waves into sample buffer for audio unit (iOS)

Given an array (of changing length) of frequencies and amplitudes, can I generate a single audio buffer on a sample by sample basis that includes all the tones in the array? If not, what is the best way to generate multiple tones in a single audio…
sphiral
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pygame Sound module for realtime synthesis

There's a python sounddevice module, which is able to synthesize a realtime audio signal frames and blocks on demand as a function of current frame time. The example usage is on the rtd:…
JonnyRobbie
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How can I force vivado to use dsp blocks for all arithmetic operations

I am trying to implement a riscv core on a ZYNQ fpga. I am doing some optimization ways to increase its performance. How can I force xilinx vivado to use DSPs for any arithmetic operation on my design?
Alaa Salman
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Do synthesis results differ between packed and unpacked arrays in SystemVerilog?

I understand the difference between packed and unpacked arrays in SystemVerilog (7.4 of the LRM). I have a two dimensional array that I can code with one of the dimensions as either packed or unpacked. Intuitively I would try to code that dimension…
WestHamster
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Using don't-care in enumeration typedef in synthesizable SystemVerilog

I have the following code: typedef enum logic [1:0] { CMD1 = 2'b1?, CMD2 = 2'b01, CMD3 = 2'b00 } cmd_t; Basically, if the MSB is 1, it's CMD1 (I'll use the LSB for part of the index). And if the MSB is 0, then decode the rest of bits for the…
jkang
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"Dead code" in Xilinx

I have some VHDL code I'm writing for a class. However, the synthesis tool identifies cell3, cell2, and cell1 as "dead" code and it won't synthesize it. I really have no idea what's going on to cause cell 3,2,1 to be removed in synthesis; I've…
Paul Nathan
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how many flip-flips would this code produce when synthesized?

I'm trying to understand how many flip-flips would this code produce when synthesized? I've got 2 test cases with non-blocking and blocking assignment code. Test 1. wire aclk; wire [1:0] a; reg [1:0] c; reg [1:0] b; always @(posedge aclk) begin…
al01
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