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We have a critical circuit at the heart of our implementation, which is the speed limiter for the entire design. It consists of just a couple dozen gates. We have implemented a custom transistor level circuit for this function by hand, done a hand-layout, and generated GDSII. We want to wire this in to our Verilog code.

The question is: how, in detail, to integrate this custom circuit with Verilog code?

Please forgive the naivete of this question. I know that the level of detail asked for is a lot. We have circuit and layout expertise on the team, but no one has integrated a custom layout with a Verilog simulator or place and route tool before. We don't really know where to start looking to find the documentation to accomplish this.

We have the GDSII of the layout, and have extracted parameters and simulated the behavior.

Now, how do we define the custom Verilog entity, such that where this entity is invoked in the Verilog code, the place and route will substitute the GDSII and the simulator will substitute the behavior?

More specifically, how do we connect our GDSII to the custom Verilog entity, such that the place and route will be aware of the GDSII file, and connect the GDSII in the right way? How do we specify signals inside the GDSII and map those to signals in our custom Verilog entity, such that the place and route will connect GDSII of Verilog wires to the appropriate GDSII ports of our hand layout?

How do we specify the behavior, and then make the simulator aware of it? Is there a special file that contains the behavior? What form does the behavior spec take, is it a truth table?

I realize this is an advanced question that may require a bit of work to spell it all out. We really appreciate any hints of where to look or what to do.

Many of you may believe us to be foolhardy and want to save us from making the mistake of doing a custom layout. Thank you for that. We have done a risk assessment and believe that the payoff in this instance is worth it. We need your help with the specifics of accomplishing the integration.

Thank you,

Sean

seanhalle
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  • Im not an expert in interfacing with external models, but I highly doubt any verilog simulator will natively support interfacing with this kind of file. My best suggestion is to create a functional model in Verilog (or CPP if you want to use DPI) independent of your design file and simulating with that (the usual strategy). If you need more precision in your simulation and have a tool that can simulate your layout, you can tie the Verilog simulation to this other simulation via pipes or sockets or something; but this will likely have to be custom code youll have to create. – Unn Dec 19 '16 at 21:18
  • The first idea that I have looking at your question in that what you want is to consider you handmade design as a library cell. In order to do what you want I would look at the way library providers describes their standard cells(verilog primitives). You can then implement you module as a standard cell directly in you design and later in the flow replace it with your GDSII. You can also define a .lib file in which is described your module and to the same as previously. You will however need a special set of license to compile the lib file to a db file with functionnality. – Krouitch Dec 20 '16 at 12:58

1 Answers1

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The problem that you are referring to is well defined & solved in the VLSI industry. The right way to solve this is to have a behavioural model (Verilog or System Verilog) for simulation purpose of the hardmacro (the circuit which is layed out as custom implementation is referred as hardmacro) and a timing model (captured in .lib view) & a physical view (captured in .lef view) for synthesis and PnR purpose.

The simulation tool will allow you to use the model for simulation purpose to verify the correctness of the design. But the accuracy of the model can only be confirmed from the reivew of how the custom circuit is modelled. If the custom circuit is simple, then modelling it is easy task. If it is analog circuit (like filters), then modelling can be difficult. The best way to verify this circuit is to do mixed signal simulation (Verilog RTL + Analog Spice), which is supported by industry standard tools.

The dot lib model is used by the synthesis and PnR tools for understanding timing requirements of the custom circuit. The dot lef view has geometry information of the custom circuit. Once PnR of standard digital circuit is complete, these tools allow import of custom GDS for replacement of the .lib & .lef view which you were using so far. This will merge the GDS for both of them.

Hope this helps.

-Sanket.

Sanket Naik
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