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Im creating an Alu, these is my code.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu is port (
    entrada: in std_logic_vector(11 downto 0);
    S: in std_logic_vector(3 downto 0);
    load : in std_logic;
    O: out std_logic_vector(12 downto 0)
    );
end alu;

architecture arc_alu12 of alu is 
    
    component sumador12bits 
        port (a, b: in std_logic_vector(11 downto 0); c: out std_logic_vector(12 downto 0));
    end component;
    
    signal sa, sb, A, aux: std_logic_vector(11 downto 0):="000000000000";
    signal sr: std_logic_vector(12 downto 0);
    
begin

    guarda_registro: process (load) begin
        if load = '1' then
            A <= entrada;
        end if;
    end process;
    
    sss: sumador12bits port map(sa, sb, sr);
    
    selector: process(S) begin
        
        case S is
            when "0000" =>
                sa <= "0000"&A(7 downto 0);
                sb <= "0000"&entrada(7 downto 0);
            when "0001" => 
                sa <= "0000"&A(7 downto 0);
                aux <= "0000"&entrada(7 downto 0);
                sb<= (not aux)+1;
            when "0010" =>
                sa <= A;
                sb <= "000000000001";
            when "0011" =>
                sa <= A;
                sb <= "111111111111";
            when "0100" =>
                sa <= entrada;
                sb <= "000000000001";
            when "0101" =>
                sa <= entrada;
                sb <= "111111111111";
            when "0110" =>
                sa <= A;
                sb <= entrada;
            when "0111" => 
                sa<=A; 
                sb<= (not entrada)+1; 
            when "1000" =>
                sr <= '0'&(A and entrada);
            when "1001" =>
                sr <= '0'&(A or entrada);
            when "1010" =>
                sr <= '0'&(A xor entrada);
            when "1011" => 
                sr <= '1'&not A;
            when "1100" =>
                sa <= not A;
                sb <= "000000000001";
            when others => sr<= "0000000000000";
        end case;
        
    end process;
    
    O <= sr;

end arc_alu12;

But I recive this message error:

@A: BN321 |Found multiple drivers on net O[0] (in view: work.alu(arc_alu12)); if one driver is a constant (true or false), use Resolve Mixed Drivers option to connect the net to VCC or GND.

Connection 1: Direction is (Output ) pin:s inst:sss.FA1.ss1 of work.semisumador(syn_black_box)

Connection 2: Direction is (Output ) pin:Q[0] inst:selector.sr[0] of PrimLib.latr(prim)

ERROR - BN314 :"e:\lscc\diamond\3.12\bin\nt64\alucode.vhd":6:7:6:9|Net O[0] (in view: work.alu(arc_alu12)) has multiple drivers

Alessia Houston
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  • 4
  • Search terms on Stackoverflow would be *[vhdl] multiple drivers*. You'd be surprised what you'd find. Here provide a [mcve] to show all the drivers. There are drivers for sr in process selector and the instantiated sumador12 bits labeled sss the source which you don't provide. It's perfectly legal in VHDL to have multiple drivers for a resolved type (std_logic, std_logic_vector). It's not legal in general in FPGA synthesis (there can be rules for how to infer multiplexers w hich you don't). –  May 26 '21 at 05:48
  • Every signal assignment occurs in a process creates a driver. Concurrent statements assigning signals elaborate processes. The value of a net of a resolved type is determined by resolution. For FPGA synthesis that is only allowed for pins and tools for particular devices that infer multiplexers from internal nets that have only one driver supplying a logic value and any others driving 'Z' (high impedance). Every other use should see signals driven from a single process, a synthesis requirement and not part of the VHDL language itself. –  May 26 '21 at 21:53

1 Answers1

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Signal "sr" connected to output port of "sumador12bits" and also you use it signal for assignment in "selector" process. This is multiple driving of one signal

Ivan Bk
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  • 2