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I have got two identical (by means of simulation) flip flop process in verilog.

First is just a standard description of register with asynchronous reset (CLR) and clock (SET) with data in tied to 1:

always @(posedge SET, posedge CLR)
if (CLR)
    Q <= 0;
else
    Q <= 1;

second one is the same as above but with second if condition for SET signal:

always @(posedge SET, posedge CLR)
if (CLR)
    Q <= 0;
else if (SET)
    Q <= 1;

There is no differences between these two implementations of flip-flop in simulation. But what does the verilog standard says about this cases? Should these tests be equivalent as well as their netlists after synthesis process?

J. Doe
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  • verilog standard says nothing about the styles of the flops. It allows you to create and simulate whatever you wish. For the rest you need to run a synthesizer and compare the netlists. Most likely they should be identical after optimization. – Serge Jan 08 '19 at 21:51
  • The question may be: if comes positive edge of SET, value of SET is already 1 or still 0? I think the best realization of this code is DFF with clk and ce tied to SET with asynchronous reset connected to CLR. – J. Doe Jan 09 '19 at 13:11
  • after posedge it will be '1'. – Serge Jan 09 '19 at 14:11
  • but how about in time of posedge? I supposed that value of SET can't be determined during posedge so in my opinion the best realization will be DFF with clk and ce tied to SET with asynchronous reset connected to CLR. Do you agree with me? Unfortunately, in the hardware the results will be different than simulation because rising edge of clock will be earlier than value 1 on clock enable (in simulation they are simultaneously) - so it look like in hardware the output will be constant zero. – J. Doe Jan 09 '19 at 14:24
  • Can you model the flop in the way you describe it? Sorry, my electrical skills are rusty, but as far as i understand, if you have enough level of SET to trigger the flop, then, unless you have unreasonable delay, it is supposed to switch the following mux as well. So, it is up to synthesizer, timing, and other tools to provide/guarantee correct HW behavior. I guess you have to try it and at least run spice simulation. – Serge Jan 09 '19 at 15:07
  • The clock path is faster than clock enable path, therefore rising clock edge will latch CE when is still 0. – J. Doe Jan 09 '19 at 15:21
  • I bet this issue had been resolved multiple times. Asynchronous flops are around for ages, so they have to be synthesized correctly. you need co consult the provider of your synthesis tool or the creators of libraries. – Serge Jan 09 '19 at 16:00
  • This is not fault of synthesis tool IMO, this is rather bad description of module in HDL. – J. Doe Jan 09 '19 at 17:00

1 Answers1

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The "if (SET)" in your second example is redundant and would be optimized away n synthesis. Since the always block will only be entered on a posedge of SET or CLR, the else statement implies that a posedge of SET has occurred.

Incidentally, the first example is a much more accepted version for coding flip flops. I've yet to see the second version make it into a shipping design.

Barry Moss
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  • I am not sure about redundancy in second example. I think it should be rather a flip flop with SET connected to clk and to ce port, not just a flip flop with SET connected to clk port. It means that in hardware after synthesis there will be no situation when rising edge of clock occurs when CE is 1 (differently than simulation). – J. Doe Jan 09 '19 at 11:03
  • I decided to try this out in Vivado. The synthesis results placed connected the SET input to the clock input on the FF and the CLR to the CLR input as I expected. However, it is possible that you might get the result you described with a different synthesis engine and depending on the component library as well. The simulation matches the behaviour of a clocked FF with a asynch clr. The always block triggers on rising edges of CLR or SET, and if CLR is asserted, the Qis forced to zero (asynch clr) but if CLR is deasserted, then a rising edge of SET causes Q to be set to 1. – Barry Moss Jan 10 '19 at 22:33