3

I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000;). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using ModelSim). For example I would like something like:

if(IN_SIM) begin
parameter SPI_RATE = 2_000_000;
end
else begin
parameter SPI_RATE = 1_000_000;
end

Thanks!

Matthew Taylor
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MRm
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4 Answers4

3

Yes, that's possible. SystemVerilog supports conditional compiler directives such as `ifdef, `ifndef, `else, `elsif, and `endif. Note that those directives are using a grave accent (ASCII 0x60) and not a normal apostrophe (ASCII 0x27).

Furthermore, most synthesis tools support the macro identifier SYNTHESIS. So, you could do the following:

`ifdef SYNTHESIS
  parameter SPI_RATE = 1_000_000;
`else
  parameter SPI_RATE = 2_000_000;    
`endif
Silicon1602
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  • It sounds exactly like what I meant! :) Thanks! I've searched a bit and haven't found anything like this in Synopsys synplify pro, have any idea how it may be called there? – MRm Apr 01 '20 at 06:15
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    Take a look in the "Synopsys FPGA Synthesis Language Support Reference Manual" and search for "synthesis macro". The manual states that Synplify Pro supports the `SYNTHESIS` macro. – Silicon1602 Apr 01 '20 at 07:35
0

Yes. You can set a macro from the command line in any simulation using the +define plusarg, eg:

+define+SPI_RATE=2_000_000

Then somewhere in your code, you can say

parameter SPI_RATE = `SPI_RATE;

And in your synthesiser there will be a mechanism for setting the value of a macro: read the instructions for your synthesiser.

Matthew Taylor
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0

IMHO -

Using the first answer

`ifdef SYNTHESIS

is much preferred over the 3rd answer

/* synthesis translate_off */

The last form is a variation of /* synopsys translate_off */, which was unique to one synthesis tool.

The macro SYNTHESIS has been in common use for more than a decade, and should be defined by any synthesis tool, without any extra command line options.

If you want to run equivalence checking (rtl vs gate level netlist), you will probably need to define the SYNTHESIS macro by the method recommended for that equivalence tool.

GregU
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-2

With Synplify Pro, you can use the /*synthesis translate_off */ /*synthesis translate_off */ to accomplish this, a similar construct is usable in VHDL with appropriate syntax/comment changes. Xilinx Vivado uses // synthesis translate_off and // synthesis translate_on

const logic IN_SIM = 1'b0
/*synthesis translate_off */
    || 1'b1
/*synthesis translate_on */
    ;

The advantage of this construct is that it doesn't require any external scripting changes.

StanOverflow
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  • You should avoid using any translation directives. It causes sim/synth mismatches. Besides this solution is not good for non-0 parameter and is just a hack. – Serge Apr 01 '20 at 15:41
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    @Serge did you read the question? That is the whole point, to produce different behaviour in simulation and synthesis, it can be used to produce any number you desire using the simple if else OP used in his code – StanOverflow Apr 02 '20 at 10:48
  • yes, i did. OP has a bad methodology decision. It is a bad methodology to use synthesis directives in any case. It is also a programming hack in your case. – Serge Apr 02 '20 at 12:31